COMPONENT CREATION - NISHUNISARGA/UVM_notes GitHub Wiki

IF WE WANT TO ADD NEW COMPONENTS(CLASSES) FOLLOW BELOW STEPS:

---

• extends from the uvm_bases class for the respective component

• factory registration

     `uvm_component_utils(class_name)     ->  for components
                 OR
     `uvm_object_utils(class_name)        ->  for objects
  

• add a new function

           function void new(string name, uvm_component parent);
                 super.new(name,parent);
           endfunction
  

• create a lower component in build_phase using type_id::create

      function void build_phase(uvm_phase phase);
          `uvm_info("top_module","hello",UVM_LOW);      -> displaying hello using uvm macro
           env = apb_env::type_id::create("env",this);   ->  env is created and registered to database of factory and "env" indicate name and this indicates present class(indicating as env's parent class)
     endfucntion
  

• connecting different components needs to be done in the connect_phase in the previous component(connect in parent class)

• create objects like transaction classes and register to the factory and also register the properties/fields/variables of the object component to the factory

• to print the structure of tb, you need to call the uvm_top.print_topology in end_of_elaboration_phase

     function void end_of_elaboration_phase(uvm_phase phase);
           uvm_top.print_topoplogy();
                   OR
          `uvm_info("TB hierarchy(sprint)",this.sprint(),UVM_NONE);     -> sprint will also print the hierarchy but serves different purpose(check the different page regarding this)
    endfunction 
  

NOTE: for randomization of packets/tx we have to use, uvm_do and uvm_do_with (if we have the inline constraint) example: uvm_do(req); or uvm_do_with(req,{req.wr_rd == 1});

      here req is the tx/packets