CHAPTER 1

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INTRODUCTION AND RUNNING UVM IN DIFFERENT TOOLS

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EDA PLAYGROUND

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• select the uvm 1.2 for running the UVM code in the EDA.

• include the MACROS for the code.

• import the uvm package to code.

  `include "uvm_macros.svh"
  import uvm_pkg::*;
  
  module tb;
    initial begin 
       $display("HOLLA!");
       `uvm_info("TOP","HELLO = HOLLA",UVM_LOW);
    end 
  endmodule
  

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VIVADO

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• run the vivado. once the vivado starts click on a new project and next.
• Then select the directory and give the project name and click next.
• select the rtl project type and click next.
• then in the port tab, select the choose the device which doesn't require any licence.(ARTIX-7 AC701)
• then click next and finish.
• In the project summary window, goto the target language choose the verilog(by default it will be having VHDL), then click apply and OK
• keep the simulator languages as mixed itself
• goto source window, choose the simulation source click on + button and select add or create simulation sources and click next.
• In the add sources window, we can add existing files or entire the directory or we can create a new file.
• if we are creating a new file, keep the file type as system verilog and give the name to the file and select the location, click ok and finish.
• the file will be automatically added sv file in sources, now we can add input/output ports for module if needed and click ok.
• now goto source double click on the file that just we add then the file will be open we can write our code
• save the code and now click on setting in tabbar, now select the simulation left corner.
• In simulation window, in compilation, for "xsim.complie.xvlog.more_option" we have to specify -L uvm and click apply. then in elaboration, for xsim.elaboration.xelab.more.option we have to specify -L uvm and click apply and click ok.
• now will run the code, in the left select the simulation then click Run simulation and choose Run behavioral simulation.
• we can observe the output in the console.