Attributes - Minres/CoreDSL GitHub Wiki

Register attributes

[[is_pc]] marks a register as the program counter.
[[is_main_reg]] marks a register file as the core's "main" register file, e.g. comprising x0-x31 in the RISC-V ISA.

[[is_main_mem]] marks an address space as corresponding to the core's main memory.

[[enable=<condition>]] indicates that the instruction is only active if condition (which may incorporate architectural state) evaluates to true.
[[format=<name>]] documents the instruction format, e.g. to be checked by downstream tools.
[[expected_encoding_width=<n>]] ensures that the binary encoding comprises exactly n bits. This attribute is most useful when attached to an instructions section.
[[no_cont]] marks an instruction as changing the control flow e.g. a jump or raising a trap.
[[cond]] marks an instruction as conditionally changing the control flow e.g a conditional jump.
[[flush]] indicates an instruction changing the instruction memory.
[[hls]] enables automatic hardware synthesis for an instruction.

[[do_not_synthesize]] directs a hardware synthesis tool to replace a call to a function with this attribute with an instance of a user-provided IP core with the same semantics as the function's body. The body can be used for simulation and verification purposes.

unsigned<32> fsin(unsigned<32> x) [[do_not_synthesize]] {
  // ... implementation of CORDIC algorithm
}