Topic ProcSystem - MeshSr/ONetSwitch GitHub Wiki
###Intro
Zynq PS, Processing System, takes a feature-rich dual-core ARM Cortex-A9 MPCore as its heart, also includes on-chip memory, external memory interfaces, and a rich set of IO peripherals.
Major function blocks:
- Application Processing Unit (APU)
- Dual ARM Cortex-A9 MPCore CPUs with ARM v7
- 32KB instruction and 32KB data L1 caches with parity per MPCore
- 512 KB of shareable L2 cache with parity
- 256 KB of on-chip SRAM (OCM) with parity
- Memory Interfaces
- DDR Controller (Supports DDR3, DDR3L, DDR2, LPDDR-2)
- Quad-SPI Controller (Single or dual)
- (SMC) NAND controller
- (SMC) Parallel SRAM/NOR controller
- IO Peripherals
- GPIO: up to 54 GPIO signals
- Gigabit Ethernet Controllers x2
- USB Controllers x2: Each as Host, Device or OTG
- SD/SDIO Controllers x2
- SPI Controllers x2: Master or Slave
- CAN Controllers x2
- UART Controllers x2
- I2C Controllers x2
- Interconnect
- (PS Interc.) OCM interconnect
- (PS Interc.) Central interconnect
- (PS-PL I/Fs) AXI_ACP
- (PS-PL I/Fs) AXI_HP, 4 high performance/bandwidth ports
- (PS-PL I/Fs) AXI_GP, 4 general purpose ports
Zynq-7000 AP SoC Overview
###LogiCORE IP Processing System 7
This core is the software interface around the Zynq-7000 platform processing system. The Zynq-7000 family consists of an SoC style integrated PS and a PL unit, providing an extensible and flexible SoC solution on a single die. The Processing System 7 core acts as a logic connection between the PS and the PL while assisting you to integrate customized and embedded IPs with the processing system using the IP integrator.
#####Typical Configuration
v5.3 Vivado2013.4
- PS-PL Configuration
General: optionally check the firstFCLK_RESET0_NforEnable Clock ResetsDMA Controller: none in useGP Master AXI Interface: optionally check the firstM_AXI GP0 interfaceGP Slave AXI Interface: neither in useHP Slave AXI Interface: optionally check the firstS_AXI HP0 interface
-
Peripheral I/O Pins & MIO Configuration Configure these 2 tabs according to the spreadsheet zynq-ps-cfg-mio.xlsx.
-
Clock Configuration See also from the spreadsheet zynq-ps-cfg-ddr.xlsx.
| Component | Enabled | Clock Src. | Req. Freq. | Act. Freq. | Class |
|---|---|---|---|---|---|
| CPU | Yes | ARM PLL | 666.6667 | 666.6667 | Processor/Memory |
| DDR | Yes | DDR PLL | 533.3333 | 533.3334 | Processor/Memory |
| SMC | No | IO PLL | IO Peripheral | ||
| QSPI | Yes | IO PLL | 200 | 200.0000 | IO Peripheral |
| ENET0 | Yes | IO PLL | 1000Mbps | 125.0000 | IO Peripheral |
| ENET1 | No | IO PLL | IO Peripheral | ||
| SDIO | Yes | IO PLL | 50 | 50.0000 | IO Peripheral |
| SPI | No | IO PLL | IO Peripheral | ||
| CAN CLK | No | IO PLL | CAN | ||
| CAN0 MIOCLK | No | External | CAN | ||
| CAN1 MIOCLK | No | External | CAN | ||
| FCLK_CLK0 | Yes | IO PLL | 125.0000 | 125.0000 | PL Fabric Clocks |
| FCLK_CLK1 | Yes | IO PLL | 75.0000 | 75.0000 | PL Fabric Clocks |
| FCLK_CLK2 | Yes | IO PLL | 200.0000 | 200.0000 | PL Fabric Clocks |
| FCLK_CLK3 | No | IO PLL | PL Fabric Clocks | ||
| TPIU | No | External | System Debug | ||
| WDT | Yes | CPU_1X | 133.3333 | 111.1111 | Timers |
| TTC0 CLKIN0 | Yes | CPU_1X | 133.3333 | 111.1111 | TTC0 |
| TTC0 CLKIN1 | Yes | CPU_1X | 133.3333 | 111.1111 | TTC0 |
| TTC0 CLKIN2 | Yes | CPU_1X | 133.3333 | 111.1111 | TTC0 |
| TTC1 CLKIN0 | No | CPU_1X | TTC1 | ||
| TTC1 CLKIN1 | No | CPU_1X | TTC1 | ||
| TTC1 CLKIN2 | No | CPU_1X | TTC1 |
- DDR Configuration
| DDR Controller Configuration | ONS20 | ONS30 | ONS45 |
|---|---|---|---|
| Memory Type | DDR 3 | DDR 3 | DDR 3 |
| Memory Part | MT41J128M16 HA-15E | MT41J256M16 RE-125 | MT41J256M8 HX-15E |
| Effective DRAM Bus Width | 32 Bit | 32 Bit | 32 Bit |
| ECC | Disabled | Disabled | Disabled |
| Burst Length | 8 | 8 | 8 |
| Operating Freq. (MHz) | 533.33 | 533.33 | 533.33 |
| Internal Vref | Yes | Yes | Yes |
| Operation Temperature (C) | Normal(0-85) | Normal(0-85) | Normal(0-85) |
| Memory Part Configuration | ONS20 | ONS30 | ONS45 |
|---|---|---|---|
| DRAM IC Bus Width | 16 Bits | 16 Bits | 8 Bits |
| DRAM Device Capacity | 2048 Mbits | 4096 Mbits | 2048 Mbits |
| Speed Bin | DDR3_1066F | DDR3_1066F | DDR3_1066F |
| Bank Address Count (Bits) | 3 | 3 | 3 |
| Row Address Count (Bits) | 14 | 15 | 15 |
| Col Address Count (Bits) | 10 | 10 | 10 |
| CAS Latency (cycles) | 7 | 7 | 7 |
| CAS Write Latency (cycles) | 6 | 6 | 6 |
| RAS to CAS Delay (cycles) | 7 | 7 | 7 |
| Precharge Time | 7 | 7 | 7 |
| tRC (ns) | 49.5 | 48.9 | 49.5 |
| tRASmin (ns) | 36.0 | 35.0 | 36.0 |
| tFAW (ns) | 45.0 | 40.0 | 30.0 |
| Training/Board Details | ONS20 | ONS30 | ONS45 |
|---|---|---|---|
| Write Leveling | checked | (ignored) | checked |
| Read Gate | checked | (ignored) | checked |
| Read Data Eye | checked | (ignored) | checked |
| DQS0 (ns) | 0.025 | (ignored) | 0.121 |
| DQS1 (ns) | 0.028 | (ignored) | 0.234 |
| DQS2 (ns) | -0.009 | (ignored) | 0.341 |
| DQS3 (ns) | -0.061 | (ignored) | 0.449 |
| DQ[7:0] (ns) | 0.410 | (ignored) | 0.393 |
| DQ[15:8] (ns) | 0.411 | (ignored) | 0.450 |
| DQ[23:16] (ns) | 0.341 | (ignored) | 0.502 |
| DQ[31:24] (ns) | 0.358 | (ignored) | 0.557 |
| Additive Latency (ns) | 0.000 | (ignored) | 0.000 |
- SMC Timing Calculation
Nothing to change. Use the default settings.
- Interrupts
Nothing to change. Use the default settings.
Notice that theIRQ_F2P16-bit shared interrupt port from PL to PS is very important when implementing more complicated project.
###LogiCORE IP Processor System Reset Module
This core is a soft IP that provides a mechanism to handle the reset conditions for a given system. The core handles numerous reset conditions at the input and generates appropriate resets at the output. This core generates the resets based upon external or internal reset conditions.