Topic Ethernet 1G - MeshSr/ONetSwitch GitHub Wiki

###PHY

#####Broadcom BCM5464SR ONS20 ONS45

• Mode Select
  • INTF_SEL[3:0]=4b0001, EN_RTBI=0, MAC interface is RGMII to Copper, 2.5V OVDD
  • ANEN=1, F1000=1, SPD0=0, Auto-negotiate advertise:10/100/1000BASE-T
  • GTXCLKDLY=x, RXCDLY=x, int. pull-downs, disable the GTXCLK input delay and the RXC output delay in RGMII to Copper mode.
• PHY Address
  • MDIO_SEL[1:0]=2b00, use the first MDIO/MDC to access all 4 ports
  • PHYA_REV=x, int. pull-downs, no reverse in PHY address numbering
  • PHYA[4:0]=5bxxxxx, int. pull-downs, i.e., all-zeros

ONS20	Left	<<--	-->>	Right
Mark	JPH1-D	JPH1-C	JPH1-B	JPH1-A
PHYAD	0	1	2	3
Linux	ETH1	ETH2	ETH3	ETH4

ONS45	Left	<<--	-->>	Right
Mark	JPH1-A	JPH1-B	JPH1-C	JPH1-D
PHYAD	3	2	1	0
Linux	ETH4	ETH3	ETH2	ETH1

To determine the Left or Right? - look at the Quad RJ45 MagJack with the Zynq face up.
Marks from A to D are always on the other side of the Quad RJ45 MagJack.
The numbering of ETHx in Linux is shown under our pre-built devicetree settings, not a fixed naming method.

#####Vitesse VSC8574 ONS30

• Mode Select
  • Mode Select for this PHY device should be done by register programming.
• External PHY Address for VSC8574
  • Only 1 pair of MDIO/MDC pins for all 4 ports
  • PHYAD[4:2]=3b100, i.e., the full address should be 5b100xx
  • Boardcase write to all the ports only if the Reg22.0 bit is set.
• Internal PHY Address for Xilinx PCS/PMA
  • Be configured during the customization of the AXI Ethernet for SGMII over LVDS.
  • Typically we set all the internal PHYADs to a unique number for simplicity.
  • Avoid to use all-zeros (broadcast PHY address) since the Xilinx PCS/PMA allows the broadcast write.

ONS30	Left	<<--	-->>	Right
Mark	JPH1-A	JPH1-B	JPH1-C	JPH1-D
Ext. PHYAD	0x10	0x11	0x12	0x13
Int. PHYAD	0x5	0x5	0x5	0x5
Linux	ETH1	ETH2	ETH3	ETH4

To determine the Left or Right? - look at the Quad RJ45 MagJack with the Zynq face up.
Marks from A to D are always on the other side of the Quad RJ45 MagJack.
The numbering of ETHx in Linux is shown under our pre-built devicetree settings, not a fixed naming method.

###LogiCORE IP AXI Ethernet
This core provides additional functionality and ease of use related to Ethernet. Based on the configuration, this IP creates interface ports, instantiates required helper cores, and also connects these cores. Helper cores for this IP are the Xilinx LogiCORE IP Tri-Mode Ethernet MAC (TEMAC) and Xilinx LogiCORE IP Ethernet 1000Base-X PCS/PMA or SGMII. Additional functionality is provided using the axi_ethenet_buffer helper core.

#####LogiCORE IP Ethernet 1000Base-X PCS/PMA or SGMII
A fully verified solution for generating Ethernet 1000BASE-X Physical Coding Sublayer/Physical Medium Attachment (PCS/PMA) or Serial Gigabit Media Independent Interface (SGMII) core.

#####LogiCORE IP Tri-Mode Ethernet MAC
The Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mb/s, 1 Gb/s and 10/100 Mb/s IP (Intellectual Property) cores along with the optional Ethernet AVB Endpoint which are fully-verified designs.

#####Typical Configuration
v6.0 Vivado2013.4

• Physical Interface - RGMII - ONS20 ONS45

• Physical Interface - SGMII - ONS30
  • Choose a number, e.g. 5, for MDIO PHY Address
  • Check to Enable Standard I/O (LVDS) for SGMII instead of a transceiver

• MAC Features
  • Check to Enable statistics counters
  • Select 32bit for Statistics Counter Width

• FIFO & Checksum
  • 4k memory size for both Rx/Tx FIFO
  • No Checksum Offload for either

• Networking Timing

• Shared Logic
  • Select Include Shared Logic in Core for the 1st 1G port.
  • Select No Shared Logic in Core for the remaining 3 1G ports.