Topic DMA - MeshSr/ONetSwitch GitHub Wiki

###Intro
DMA, Direct Memory Access, allows certain hardware subsystems to access main system memory (RAM) independently of the central processing unit (CPU).

###LogiCORE IP AXI DMA
The AXI Direct Memory Access (AXI DMA) IP provides high-bandwidth direct memory access between the AXI4 memory mapped and AXI4-Stream IP interfaces. Its optional scatter gather capabilities also off load data movement tasks from the Central Processing Unit (CPU) in processor-based systems. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface.

#####Typical Configuration
v7.1 Vivado2013.4

• Tab for all settings
  • Check Allow Unaligned Transfers for Enable Read Channel
  • Check Allow Unaligned Transfers for Enable Write Channel
  • Check Use Rxlength In Status Stream for Enable Write Channel