ONetSwitch30 - MeshSr/ONetSwitch GitHub Wiki

###Overview ONetSwitch30 is a Quad Gigabit Ethernet Ports SBC based on Xilinx XC7Z030, which combines the software programmability of ARM processors with the hardware programmability of FPGAs. With a FPGA programmable accelerator, five Gigabit Ethernet ports, Up to 3GB DDR3 DRAM, GPIO, and Mini PCIe Slot for WLAN Card or SSD Card.

###Features

• General
  • Main Silicon XC7Z030-2SBG485
  • Power Supply DC 12V
  • Primary Config. TF card
  • Auxiliary Config. QSPI flash/JTAG
• Processing System
  • Processor Dual ARM Cortex-A9@800MHz
  • Cache (L1)32KB Inst. + 32KB Data per core; (L2)512KB; (OCM)256KB
  • DRAM DDR3 1GBytes
  • Flash Quad SPI flash 256Mb
  • DMA 8 channel (4 for Programmable Logic)
  • Ethernet 1x GE RJ45
  • Peripherals USB / USB-UART / USB JTAG / TF card
• Programmable Logic
  • FPGA Logic 125K LCs, Kintex-7, ~1.9M ASIC gates
  • Host I/F AMBA AXI4 interconnect, max 100Gbps between PS-PL
  • DRAM DDR3 2GBytes
  • Ethernet 4x GE RJ45
  • Peripherals 2x PMOD
  • User IO user LEDs/push buttons/DIP switch
  • Extension mini PCIe for wireless NIC or SSD

###Block Diagram

###Board Layout

###Specification For details of the board hardware, please download the ONetSwitch30 Hardware User Guide.