Guide Hardware Design - MeshSr/ONetSwitch GitHub Wiki

Intro

The design for ONetSwitch hardware, i.e. the FPGA part as Programmable Logic, commonly follows a Xilinx Vivado flow.
Here we provide a reference tcl script and folder structure, which show a guideline to manage the project generation and organization in Vivado, with IP package and block design integration.
All of our Getting-Started projects and reference designs are organized in this way.

Tcl Script

Project Root

The folder is assigned as the ROOT, when it originally contains following

  • myproj (folder) stores all the design sources and tcl.
  • myproj.tcl (script) to generate the project.
IP Designs

All the design sources of user IPs are listed in the folder ROOT/myproj/ip.
The IPs should be managed in each subfolder, e.g.,
ROOT/myproj/ip/my_ip_0, ROOT/myproj/ip/my_ip_1, ... ROOT/myproj/ip/my_ip_n

In each IP folder, e.g., ROOT/myproj/ip/my_ip_n, contains typically

  • src (folder) contains all design sources - hdl, netlist..
  • my_ip_n.tcl (script) to package single IP to a zip for an IP-repository.

To generate or modify my_ip_n.tcl, please follow the Vivado IP flow.

IP Repository

The script myproj.tcl fetches the ip_list and then sources all the my_ip_n.tcl, storing the zip in a newly created folder ip-repo in the ROOT.
The ip-repo is a runtime folder for IP generation and package.

Modify the ip_list variable in "myproj.tcl" to add IPs to your block design.

Block Design

Only one block design can be supported in this tcl script.
The system block design can be created by sourcing ROOT/myproj/bd/myproj_bd.tcl
The myproj.tcl automatically generates the wrapper for the block design.

The myproj_bd.tcl can be generated by running write_bd_tcl after a complete block design in Vivado. Please follow Vivado tcl scripting guide for details.

Sources and Constraints

Common hdl, netlist and constraint files can be stored and organized in ROOT/myproj/sources and ROOT/myproj/constrs
Hierarchical folder structure is allowed.

Simply modify the source_files and constr_files variables in myproj.tcl to add these sources to your design.

Project Generation

In the Vivado tcl shell, change directory to the ROOT and simply source the tcl. e.g.,

cd ROOT
source myproj.tcl

The tcl collects all IPs, blockdesign(s), common hdl/netlist/constraints and then generates the project.
Synthesis and implementation flows can be added after that.

Project Cleanup

Manually (and carefully) delete all files and folders except following

  • myproj (folder) stores all the design sources and tcl.
  • myproj.tcl (script) to generate the project.