GSG QDRIIMemTest - MeshSr/ONetSwitch GitHub Wiki

###Intro
This project set is for ONetSwitch45 QDRII+ only, implementing a migrated QDRII+ example design from Kintex-7 MIG2.0.

Demo runs at u-boot level.

###Project List

Board	Project
ONetSwitch20	N/A
ONetSwitch30	N/A
ONetSwitch45	ons45-gsg-5-mqdr_test

###Pre-Built Images

• For quick start demo.

File	ONetSwitch20	ONetSwitch30	ONetSwitch45
boot.bin	N/A	N/A	Download
devicetree	N/A	N/A	N/A
kernel	N/A	N/A	N/A
rootfs (FAT)	N/A	N/A	N/A
sw-lib	N/A	N/A	N/A
sw-app	N/A	N/A	N/A

• For image assembling.

File	ONetSwitch20	ONetSwitch30	ONetSwitch45
system.bit	N/A	N/A	Download
fsbl	N/A	N/A	Download
u-boot (FAT)	N/A	N/A	Download
u-boot (EXT)	N/A	N/A	Download
rootfs (EXT)	N/A	N/A	N/A

###Design Target

1. Check the calibration-done signal for QDRII+.
2. Check the error status of the example traffic generator for QDRII+ write/read.

###Design Outline

1. VVD Create a simple ZYNQ7 system with Processing System 7 and Processor System Reset Module.
2. VVD Import the design generated by Memory Interface Generator for XC7K325T-2FFG900 device with simple pin assignment specified in the hardware spec.
3. VVD Button and LED indicators

• SW5: Manual reset.
• DS5: calibration-done, active high.
• DS6: traffic generator r/w error, active high.
• DS7: 200MHz clock from the Processing System.
• DS8: system reset, active low.

###Demo

• Prepare the images in SD/TF card, or download the pre-built ones.
• Check the LEDs, especially DS5 the calibration should be done, and DS6 there is no error shown.
• Reset it with button SW5 and then release the reset, the calibration-done would recover, no r/w error.

###Vivado2013.4
In Vivado2013.4, for ONS45, the Memory Interface Generator IP does not support QDRII+ SRAM for Zynq devices. We have to use Kintex-7 instead, take the similar bank assignment for the pins, then generate the RTL to be imported to the Zynq project, as sub module under the top.
You can build the project directly without the Memory Interface Generator IP.