GSG PCIeRootEnum - MeshSr/ONetSwitch GitHub Wiki

###Intro
This project set sets up a PCIe Root Complex inside the Zynq PL, communicating with an external wireless NIC as a demo, to show the example PCIe enumeration and the link.

Demo runs a Bare-Metal App. instead of u-boot after the FPGA programming.

###Project List

Board Project
ONetSwitch20 N/A
ONetSwitch30 ons30-gsg-4-pcie_rc_test
ONetSwitch45 ons45-gsg-4-pcie_rc_test

###Pre-Built Images

  • For quick start demo.
File ONetSwitch20 ONetSwitch30 ONetSwitch45
boot.bin N/A Download Download
devicetree N/A N/A N/A
kernel N/A N/A N/A
rootfs (FAT) N/A N/A N/A
sw-lib N/A N/A N/A
sw-app N/A N/A N/A
  • For image assembling.
File ONetSwitch20 ONetSwitch30 ONetSwitch45
system.bit N/A Download Download
fsbl N/A Download Download
u-boot (FAT) N/A N/A N/A
u-boot (EXT) N/A N/A N/A
rootfs (EXT) N/A N/A N/A
bare-metal N/A Download Download

###Target

  1. Verify the mini PCIe interface and link.
  2. Use Xilinx AXI Bridge for PCI Express IP for network applications, with Atheros AR9380 wireless NIC.
  3. Show the process of PCIe enumeration, implementing a PCIe root complex in Zynq PL.

###Block Diagram

###Design Outline

  1. VVD Create a simple ZYNQ7 system with Processing System 7 and Processor System Reset Module.
  2. VVD Add AXI Bridge for PCI Express as the PCIe root complex with correct settings.
  3. VVD Manage the data transmit (direction from host to WNIC) and controller interface of AXI Bridge for PCI Express with an AXI GP interface, using AXI Interconnect.
  4. VVD Manage the data receive (direction from WNIC to host) interface of AXI Bridge for PCI Express with an AXI GP interface, using AXI Interconnect.
  5. SDK Generate the example application as 'xaxipcie_rc_enumerate_example' from SDK templates, adapt it to the current system with adding 'init_platform' at the beginning of 'main' method, build to get the pcie_rc_enum.elf file.
  6. SDK Generate the boot.bin with FSBL(include AD9516-3 configuration), system.bit and the newly built pcie_rc_enum.elf(substitute the common u-boot).

###Demo

  • Prepare the images in SD/TF card, or download the pre-built ones.
  • Put an Atheros AR9380 WNIC into the mini PCIe slot. (For ONS30) Connect J7 to J14 with a SATA cable.
  • Power on the board, check the log printed by pcie_rc_enum.elf, notice that the vendor ID for Xilinx is 0x10EE and for Atheros is 0x168C.
*** example ***

Start Initialization of PCIe Root Complex on This System
Interrupts currently enabled are        0
Interrupts currently pending are        0
Interrupts currently enabled are        0
Interrupts currently pending are        0
Link is up
Bus Number is 00
Device Number is 00
Function Number is 00
Port Number is 00
PCIe Local Config Space is   100147 at register CommandStatus
PCIe Local Config Space is    70100 at register Prim Sec. Bus
Root Complex IP Instance has been successfully initialized
Start Enumeration of PCIe Fabric on This System
PCIeBus is 00
PCIeDev is 00
PCIeFunc is 00
Vendor ID is 10EE
This is a Bridge
PCIeBus is 01
PCIeDev is 00
PCIeFunc is 00
Vendor ID is 168C
This is an End Point
End Point has been enabled
End of Enumeration of PCIe Fabric on This system