GSG MACLoopBack - MeshSr/ONetSwitch GitHub Wiki
Intro
This project set shows the basic interconnection among the PHYs and the MACs, verifies the Zynq PL Ethernet ports as a most important feature on an ONetSwitch.
Get the Gigabit Ethernet interfaces on the board verified.
Demo runs at u-boot level.
Project List
Pre-Built Images
| File |
ONetSwitch20 |
ONetSwitch30 |
ONetSwitch45 |
| boot.bin |
Download |
Download |
Download |
| devicetree |
N/A |
N/A |
N/A |
| kernel |
N/A |
N/A |
N/A |
| rootfs (FAT) |
N/A |
N/A |
N/A |
| sw-lib |
N/A |
N/A |
N/A |
| sw-app |
N/A |
N/A |
N/A |
- Additional init./config. script.
Target
- Use Xilinx AXI Ethernet IP for network applications, as the MACs (and internal PHYs in SGMII mode).
- Connect the MACs (and the internal PHY) to the external PHYs, which are managed by the MDIO.
- Setup and test the loops at the AXI-Stream interface of AXI Ethernet IP.
- Verify the Gigabit Ethernet interfaces on the board.
Block Diagram
Design Outline
VVD Create a simple ZYNQ7 system with Processing System 7 and Processor System Reset Module.VVD Add 1x AXI Ethernet with 'Shared Logic', which instantiates the quad PLL, the MMCM, and the IDELAYCTRL. Add another 3x AXI Ethernet without 'Shared Logic'.VVD Manage all the generated AXI Ethernet with an AXI GP interface, using AXI Interconnect.VVD Connect 2 pairs of internal AXI-Stream Ctrl/Data loop, i.e., #0-#1 and #2-#3.
Demo
- Prepare the images in SD/TF card, or download the pre-built ones.
- Topo setup:
- RJ45 #0: Traffic generator/source from PC.
- RJ45 #1-2: Loop.
- RJ45 #3: Traffic monitor/sink to PC.
- Configure the registers inside PHY devices for initialization.
- Check the statistic counters - all zeros.
- Send certain number of packets from the generator and capture them on the monitor.
- Check the statistic counters - the Rx/Tx counters from all the MACs and the generator/monitor should be the same.
