PLL in HDL - Maverick-Shark/retroGuru GitHub Wiki

Info

• Wiki- Phase-locked loop

PLL parameters

Fref = Fin/N 
Fvco = Fin(M/N) 
Fout = Fin(M/(N*C)) 

Fref = Fin/N        = 
Fvco = Fin(M/N)     =  Fref*M
Fout = Fin(M/(N*C)) = (Fref*M)/C = FVco/C = (Fin*M)/(N*C)

objF = ((Fin*(M+Mdec)/(N*C))-Fout)^2 

• Example:

for (n=1; n<n_max; n++) 
for (c=1; c<c_max; c++) 
for (m=1; m<m_max; m++) 
calculate frequency and compare 
exit if result is ok 

• How to calculate PLL parameters

Tutorials

• Introduction to FPGA Part 9 - Phase-Locked Loop (PLL) and Glitches | Digi-Key Electronics:

Links

• Logic PLL