u‐boot mmu - MarekBykowski/readme GitHub Wiki
How it works
Set breakpoint, then run to it
hbreak -p cache_v8.c:setup_all_pgtables
cont
Print translation table at EL2N
pointed to from TTBR0_EL2
mmu list tables
mmu print EL2N_S1_TTBR0_EL2
mmu list memory-maps
mmu memory-map EL2N_S1
Should be invalid as the translation tables haven't been set yet.
Read the page table address from u-boot printout, set a watchpoint
there and print the memory afterwards
watch *0xfeff0000
x /4g 0xfeff0000
Upon filling in the translation tables x /4g 0xfeff0000
should return
EL2N:0x00000000FEFF0000: 0x0060000000000401 0x0060000040000401 0x0000000080000711 0x00000000C0000711
0x0060000000000401
is a block descriptor. Let us decipher it. Bits [54], [53], [10], [0] are set. OA (Output Address) noted below is on bits [47:42]. These are 0 so that VA
0 translates to PA
0 with the attributes XN=1, AF=1, SH=0x0, AP=0x0, Indx=0x0. What we have got left is to read the MAIR_EL2
to which the Indx
=0x0 points to.
print /x $MAIR_EL2
MAIR_EL2
should be 0xFF440C0400 and our Indx
=00 points to the first 8-bit chunk which is 0b0000000
. All the zeros is Device memory
Print translation table at EL2N
pointed to from TTBR0_EL2
mmu print EL2N_S1_TTBR0_EL2
mmu memory-map EL2N_S1
Use u-boot's API
U-boot defines a static mapping of the translation tables with the desired mapping and attributes. See here board/armltd/vexpress64/vexpress64.c
static struct mm_region vexpress64_mem_map[] = {
{
.virt = V2M_PA_BASE,
.phys = V2M_PA_BASE,
.size = SZ_2G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = V2M_DRAM_BASE,
.phys = V2M_DRAM_BASE,
.size = SZ_2G,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/*
* DRAM beyond 2 GiB is located high. Let's map just some
* of it, although U-Boot won't realistically use it, and
* the actual available amount might be smaller on the model.
*/
.virt = 0x880000000UL, /* 32 + 2 GiB */
.phys = 0x880000000UL,
.size = 6UL * SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* List terminator */
0,
}
};