Gatesim Flow - Maosishidy/CXL-PCIe GitHub Wiki

GateSim Flow & Notes

  1. GateSim Introduction GateSim can help chip to verify dynamic circuit behavior. In our project, GateSim run two type cases which include without SDF and with SDF.
  2. GateSim without SDF
  3. Prepare Filelist There are two main part in the filelist. The First Part is stand cell and the second part is pre-layout of RTL.

Set bj.scons point to gatesim filelist without sdf

  1. Prepare Deposite Cell  The X status will be transferred in GateSim. Thus some cells whose initial state are X should be deposite to prevent X status to transferring.
  2. Non-reset flop
  3. SRAM Q pin flop
  4. Sync_dpin: data pins of data synchronizer
  5. Sync_rpin: aysnc pins of reset synchronizer Pnitial state of the pins above four type are X status. There is auto deposite script to change pins list file to be used by DV env. The dir of this script:

Usage:

 Use ucli to do deposite

  1. Make sure “+debug_access+all” has been add in compile option.

  2. Use ucli –do host_ep_subsys.do to deposite data.

  3. config option Below lists two special options which are related to timing.

  4. +nospecify

  5. +notimingcheck These two options can improve gatimesim without sdf and prevent x status transfer.

  6. GateSim with SDF

  7. Prepare Filelist StandCell is the same as GateSim without sdf. Netlist should use post-layout netlist

Set bj.scons point to gatesim filelist without sdf

  1. Prepare notimingcheck flop X status will happen when first flop of sync and 2nd/3rd flop of rst_sync and pulse flops are toggled. So these flops should be set notiming check to prevent X status transfer. There are three type notimingcheck flops in our project.
  2. Common cells which will be provided by feint. This type list can be solved by scripts (auto_notiminglist.py) to convert this list to notimingcheck file. Dir:

Usage:

Below screenshot shows notimng cell and notiming cfg file.

  1. special timing async first flop These flops should be provided by DE.
  2. phy model notimingcheck flop These flops are extracted from phy sdf. For example, notimingcheck flops extracting method of pcie phy model is descibed in section 3.1.1 of “DesignWare Cores High Speed SerDes Gate-Level Simulations”

 Config notiming flop to DUT

Note:

  1. sdf and netlist version should match
  2. deposite cell should be used
  3. config option GateSim with sdf should remove +nospecify +notimingcheck.