SPI‐PROTOCOLS - KotlaChenna/I2C-AND-SPI-PROTOCOLS-DESIGN-USING-VERILOG GitHub Wiki
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Standard SPI is a high-speed, full-duplex, synchronous communication bus [4]. For
saving the chip ports and space on PCB layout, the ports of the SPI only take four lines.
It is working in the Master-Slave full duplex mode which has one master device and one
slave device and requires four lines whose components are SDI (data in), SDO (data out),
SCK (clock), SS (Slave select) .When the SPI master wants to send data to a slave, it will
pull the SS line low for selecting slave, and activates the clock signal which usable
between the master and the slave at same time. The master transmits the data to the
MOSI (master’s SDO and slave’s SDI) line and receives the data from the MISO
(master’s SDI and slave’s SDO) line at the time. SPI is a serial communication protocol,
that data is transmitted bit by bit. The clock pulse is provided by SCK and SDI, SDO is
based on this pulse to making the data transmission. Data output through the master’s
SDO line at the rising or falling edge of the clock and be read by slave in the falling or
rising edge followed. So 8-bit data transfer need at least 8 times the clock signal changes
SPI Signal Descriptions:
Master In Slave Out (MISO)
The MISO line is configured as an input in a master device and as an output in a slave
device. It is one of the two lines that transfer serial data in one direction, along with the
most significant bit sent first. The MISO line of a slave device is placed in the highimpedance state if the slave is not selected.
Master Out Slave In (MOSI) The MOSI line is configured as output in a master device
and as an input in a slave device. It is one of the two lines that transfer serial data in one
direction, with the most significant bit sent first
Serial Clock (SCK) The serial clock is used to synchronize data movement both in and
out of the device through its MOSI and MISO lines. The Master and Slave devices are
capable of exchanging a byte of information during a sequence of eight clock cycles.
Since SCK is generated by the master device, this line becomes an input on a slave
device.
Slave Select (SS bar) The slave select input line is used to select a slave device. It has to
be low prior to data transactions and must stay low for the duration of the transaction.
SPI DATA TRANSMISSION:
The SPI has four modes of operation, 0 through 3. These modes essentially control the
way data is clocked in or out of an SPI device. The configuration is done by two bits in
the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit,
which selects an active high or active low clock. The clock phase (CPHA) control bit
selects one of the two fundamentally different transfer formats. To ensure a proper
communication between master and slave both devices have to run in the same mode.
Device- Configurated Devices
Simulated Graphs-- SPI
The output graphs of SPI protocol in Xilinx vivado software :
