LP20 Printer Controller - KS10FPGA/KS10FPGA Wiki
The LP20 Line Printer System is a Unibus-based hard-copy line printer system. In this implementation, the LP20 interfaces the KS10 FPGA IO Bus to a simulated LP26 Line Printer. This design is fully register compatible with the DEC LP20 and passes all relevant diagnostics. The interface to an external printer is via a simple full-duplex RS232 connection. Handshaking uses the XON/XOFF protocol.
The LP20 Verilog implementation is fully parameterized: the base IO address and the interrupt vector are controlled by module parameters. Several LP20s could be instantiated and attached to the IO Bus Bridge (UBA) adapters - however only a single LP20 is currently instantiated in the code.
A summary of LP20 registers is shown below:
This section provides programming and implementation details of the LP20 registers.
Control/Status A Register (CSRA)
The Control/Status A Register provide general printer control and status and is both byte and word addressable.
Control/Status B Register (CSRB)
The Control/Status B Register provide general printer control and status and is both byte and word addressable.
Bus Address Register (BAR)
The Bus Address Register provides the virtual address of the DMA data. This virtual address is translated to a physical address by the IO Bus Bridge (UBA).
The Bus Address Register is word addressable only.
Byte Count Register (BCTR)
The Byte Count Register controls the length of a DMA operation. The twos-complement of the number of bytes to load is written into the BCTR. Each DMA cycle increments the BCTR. When the BCTR increments to zero, the DMA operation is complete.
The Byte Count Register is word addressable only.
Page Count Register (PCTR)
The Page Count is loaded with a prescribed number of pages – presumably the number of pages in a box of fan-fold paper. As each page is printed, the PCTR is decremented. When the PCTR is decremented to zero, the Page Count Zero (CSRA[PCZ]) bit is asserted and an interrupt is generated. Again, presumably to wake up the operator and change the paper.
The Page Count Register is word addressable only.
RAM Data Register (RAMD)
Data characters for the Translation RAM are written to the RAM Data Register.
The RAM Data Register is word addressable only.
The RAM Address Register is modified under the following conditions:
Column Counter Register (CCTR) / Character Buffer Register (CBUF)
The column counter is normally used by the DEC LP20 to implement tab characters. When a tab character is found, the LP20 replaces the tab character with a sequence of 1 to 8 spaces. Similarly, the LP20 also causes the printer to wrap text to the next line after column 132.
The Column Counter Register and Character Buffer Register are byte addressable.
Checksum Register (CKSM) / Printer Data Register (PDAT)
The Checksum Register is used to verify the integrity of DMA transfers. The Checksum Register is set to zero when the DMA operation starts and the register accumulates the data bytes during the DMA operation. When the DMA operation has completed, the checksum is reported in this register.
The Checksum Register and Printer Data Register are byte addressable.
The LP20 has four major modes: Print Mode, Test Mode, Load DAVFU Mode, and Load RAM Mode. These modes are described in the following sections.
The Print Mode is the normal mode of operation.
In Test Mode, the print characters are not printed and the printer handshake lines are looped back to the LP20. This mode behaves as-if the printer output was routed to the bit-bucket – even if a printer is not present. Optionally other hardware tests are enabled for hardware testing.
These optional tests are described in the following sections.
Normal Test Mode
In Normal Test Mode, no additional test modes are enabled. As stated above, nothing is output to the printer.
Demand Timeout Test Mode
The Demand Timeout Test Mode disables the handshake acknowledge from the printer. This causes the printer interface to timeout and assert a Demand Timeout Error (CSRB[DTE]).
In the KS10 FPGA, the Demand Timeout Error is asserted while the unit is in Demand Timeout Test Mode.
SSYN Timeout Test Mode
The SSYN Timeout Test Mode disables the DMA acknowledge from the memory subsystem. This will cause the DMA controller to timeout and assert a IO Bus Time-out Error (CSRB[MSYN]).
RAM Parity Test Mode
In RAM Parity Test Mode, the parity written to the RAM and the parity read from RAM are inverted.
A RAM parity error will occur if the RAM is written with the RAM Parity Test Mode in one state and the RAM is read with the RAM Parity Test Mode in other state.
Memory Parity Test Mode
Memory parity is not implemented. In Memory Parity Test Mode, every DMA access of memory will generate a Memory Parity Error (CSRB[MPE]).
Line Printer Parity Test Mode
Line printer parity is not implemented. In Line Printer Parity Test Mode, every printed character will generate a Line Printer Parity Error (CSRB[LPE]).
Page Counter Test Mode
The Page Counter Test Mode allows the Page Counter hardware to be tested and is enabled by setting the controller into Test Mode (set CSRA[MODE[2:0]] = 2) and selecting the Page Counter Test Mode (CSRB[TEST[2:0]]) = 6).
In this mode, Page Counter is incremented every time a ‘1’ written to the Go Error bit in the CSRB (CRSB[GOE] = 1).
Load DAVFU Mode
The Load DAVFU Mode allows the DAVFU to be updated via DMA.
Load Translation RAM Mode
The Load RAM Mode allows the Translation RAM to be updated via DMA.
A transcript of the Line Printer Diagnostic Tests is included below:
The LP20 Printer Controller and the LP26 printer emulation is stable with no known deficiencies. While the KS10 system supported printers other than the LP26, only the LP26 printer emulation is provided. The DSLPA diagnostics has provisions for testing an LP07 printer which will fail as expected because the LP07 and LP26 behave differently in some cases.