The LP20 Line Printer System is a Unibus-based hard-copy line printer system. In this implementation, the LP20 interfaces the KS10 FPGA IO Bus to a simulated LP26 Line Printer. This design is fully register compatible with the DEC LP20 and passes all relevant diagnostics. The interface to an external printer is via a simple full-duplex RS232 connection. Handshaking uses the XON/XOFF protocol.

The LP20 Verilog implementation is fully parameterized: the base IO address and the interrupt vector are controlled by module parameters. Several LP20s could be instantiated and attached to the IO Bus Bridge (UBA) adapters - however only a single LP20 is currently instantiated in the code.

A summary of LP20 registers is shown below:

LP20 Register Summary
IO Addr (Dev 1)	IO Addr (Dev 2)	Register Name	Access	Register Description
775400	775420	CSRA	Byte	Control/Status A Register
775402	775422	CSRB	Byte	Control/Status B Register
775404	775424	BAR	Word	Bus Address Register
775406	775426	BCTR	Word	Byte Count Register
775410	775430	PCTR	Word	Page Count Register
775412	775422	RAMD	Word	Translation RAM Data Register
775414	775434	CBUF	Byte	Character Buffer Register
775415	775435	CCTR	Byte	Column Counter Register
775416	775426	PDAT	Byte	Printer Data Register
775417	775437	CKSM	Byte	Checksum Register

LP20 Registers

This section provides programming and implementation details of the LP20 registers.

Control/Status A Register (CSRA)

The Control/Status A Register provide general printer control and status and is both byte and word addressable.

Control/Status Register A (CSRA)

Control/Status A Register (CSRA) - IO Address 775400
Bit(s)	Mnemonic	R/W	Description
15	ERR	R	Composite Error This bit is set when any of the following transition to active: Memory Parity Error (CSRB[MPE]), or RAM Parity Error (CSRB[RPE]), or Line Printer Parity Error (CSRB[LPE]), or Unibus Time-out Error (CSRB[MTE]), or Demand time-out Error (CSRB[DTE]), or Printer Offline (CSRB[OFFL]), or DAVFU Not Ready (CSRB[DVOF]), or Go Error (CSRB[GOE]). This bit is cleared by: Issuing and Error Clear (CSRA[ECLR] = 1), or Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an IO Bridge Clear (UBACSR[INI] = 1). Writes ignored.
14	PCZ	R	Page Counter Zero. This bit is set when the Page Counter is decremented to zero. This bit is cleared by: Writing to the Page Count Register, or Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an IO Bridge Clear (UBACSR[INI] = 1). Writes ignored
13	UNDC	R	Undefined Character This bit is set when: Mode is Load RAM Mode (CSRA[MODE] = 3), and DMA read occurs, and One or more of the following conditions exists: The output of the Translation RAM indicates Interrupt asserted (RAMD[INT] = 1) and Translate negated (RAMD[TRANS] = 0), or The output of the Translation RAM indicates Interrupt asserted (RAMD[INT] = 1) and Delimiter Hold asserted (CSRA[DHLD] = 1) and Translate asserted (RAMD[TRANS] = 1). This bit is cleared by issuing a Go Command (CSRA[GO] = 1). Writes ignored.
12	VFURDY	R	Direct Access Vertical Format Unit (DAVFU) Ready This bit is asserted when the DAVFU is loaded properly and is ready to use. The VFU is physically located in the printer. This bit is set when: The printer is configured to use an Optical Vertical Format Unit (CSRB[OVFU] = 1), or The printer is configured for a DAVFU and a START character, at least one data word (two bytes of DMA), and a STOP character is written to the DAVFU. This bit is cleared when: The LP20 is configured to load the DAVFU (CSRA[MODE] = 2) and a START character is written to the DAVFU with no corresponding STOP character, or The LP20 is configured to load the DAVFU (CSRA[MODE] = 2) and a START character is written to the DAVFU followed immediately by a STOP character (no data), or The LP20 is configured to load the DAVFU (CSRA[MODE] = 2) and a STOP character is written to the DAVFU which is not preceded by a START character. The LP20 is configured to load the DAVFU (CSRA[MODE] = 2) and a START character is written to the DAVFU and the DMA completes without transmitting a STOP character, or The printer's VFU overruns the end of the DAVFU or OVFU tape. The printer is re-configured from an Optical Vertical Format Unit to a DAVFU. The selection between an Optical Vertical Format Unit (OVFU) and Direct Access Vertical Format Unit (DAVFU) is controlled by the OVFU Field in the LP20 Console Control Register (LPCCR) (LPCCR{OVFU]). Therefore the Console Processor can select between the two types of printers. The DAVFU is physically located in the printer; therefore, resetting the LP20 does not reset the DAVFU. Writes ignored.
11	ONLINE	R	Online This bit indicates the printer online/offline status. This bit is set when the Console Processor manually commands the printer to be online by writing a '1' to the LPCCR[ONLINE] bit in the LP20 Console Control Register. This bit is cleared when: The Console Processor manually commands the printer to be offline by writing a '0' to the LPCCR[ONLINE] bit in the LP20 Console Control Register, or Any error programming the DAVFU. Specifically: Writing more than 144 words (288 bytes) to the DAVFU, or Writing an odd number of bytes to the DAVFU. The printer's VFU overruns the end of the OVFU tape or the end of the DAVFU. Writes ignored.
10	DHLD	R/W	Delimiter Hold This bit is set when the last received character was a Delimiter. This bit is set under the following conditions: Writing a one to it, or Set during a DMA read cycle as follows: DMA read cycle, and The Mode is Print Mode (CSRA[MODE] = 0) or the Mode is Test Mode (CSRA[MODE] = 1), and A Composite Error condition is not present (CSRA[ERR] = 0) , and The Delimiter Bit in the Translation RAM is set (RAMD[DEL] = 1). This bit is cleared when: Writing a zero to it, or Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an IO Bridge Clear (UBACSR[INI] = 1).
9	ECLR	W	Error Clear Asserting this bit clears the following status bits: Composite Error (CSRA[ECLR]), and Go Bit (CSRA[GO]) Memory Parity Error (CSRB[MPE]) RAM Parity Error (CSRB[RPE]) IO Bus Timeout Error (CSRB[MSYN]) Go Error (CSRB[GOE]) This bit is always read as zero.
8	INIT	W	Controller Clear. Asserting this bit does the following: Resets the Base Address Register (BAR) to zero, Resets the Column Counter Register (CCTR) to zero, Resets the Byte Counter Register (BCTR) to zero, Reset the Page Counter Register (PCTR) to zero, Clears the Delimiter Hold (CSRA[DHLD]), Clears the Interrupt Enable (CSRA[IE]) Clears the Mode (CSRA[MODE[3:2]]) Clears the Parity Test (CSRA[PAR]) Clears the Go Bit (CSRA[GO]) Sets the Done Status (CSRB[DONE]) Clears the Test Mode (CSRB[TEST[10:8]]) Setting this bit does not alter the Checksum Register (LPCKSM), the Character Buffer Register (LPCBUF), the Translation RAM, or the Translation RAM Address. This bit is always read as zero.
7	DONE	R	Done This bit indicates the status of the DMA controller. This bit is set when: Byte Counter is incremented to zero, or Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an IO Bridge Clear (UBACSR[INI] = 1). This bit is cleared when the Byte Counter is written. Writes are ignored.
6	IE	R/W	Interrupt Enable These bits are set by writing to this register. These bits are cleared by: Writing to this register, or Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an IO Bridge Clear (UBACSR[INI] = 1). When this bit is asserted, the following conditions will cause an interrupt: Composite Error (CSRA[ERR] = 1), or Page Zero (CSRA[PCZ] = 1), or Undefined Characters (CSRA[UNDC] = 1), or The DMA completes (CSRA[DONE] = 1). DAVFU Ready (CSRA[DVON]) changes state, or On-line (CSRA[ONLINE]) changes state.
5-4	ADDR	R/W	Bus Address Extension [17:16] These bits are set by writing to this register. These bits are cleared by: Writing to this register, or Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an IO Bridge Clear (UBACSR[INI] = 1).
3-2	MODE	R/W	Mode These bits are set by writing to this register. These bits are cleared by: Writing to this register, or Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an IO Bridge Clear (UBACSR[INI] = 1). The LP20 Modes are:
			0	Print Mode This mode allows data to be printed via DMA.
			1	Test Mode This mode allows data to be printed via DMA. Except it is never printed.
			2	Load DAVFU Mode This mode allows the DAVFU to be loaded via DMA.
			3	Load RAM Mode This mode allows the translation RAM to be loaded via DMA.
1	PAR	R/W	Parity Test Enable When asserted, this bit enables the following parity errors to be reported as errors, otherwise they are ignored. Translation RAM Parity Errors, and Line Printer Parity Errors, and Memory Parity Errors. This bit is set by writing one to this register. This bit is cleared by: Writing zero to this register, or Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an IO Bridge Clear (UBACSR[INI] = 1).
0	GO	R/W	Go. This bit starts a DMA transfer from KS10 memory to the LP20. This bit is set and DMA will start when: Writing one to this register, and Composite Error (CSRA[ERR]) is not asserted. This bit is cleared and DMA will stop when: Writing zero to this register, or The Byte Counter increments to zero (CSRA[DONE] = 1), or The Page Counter decrements to zero (CSRA[PGZ] = 1),or An Undefined Character (CSRA[UNDC]). If an Composite Error (CSRA[ERR]) condition exists at the time this command is issued: the DMA operation will not start, and the GO Error indication (CSRB[GOE]) will be indicated. Note: CSRA[GO] must be asserted after all of the other bits in CSRA are set to the desired state. Changing the register contents simultaneously with setting the GO bit can result in undefined behavior.

Control/Status B Register (CSRB)

The Control/Status B Register provide general printer control and status and is both byte and word addressable.

Control/Status Register B (CSRB)

Control/Status B Register (CSRB) - IO Address 775402
Bit(s)	Mnemonic	R/W	Description
15	VAL	R	Valid Data This bit toggles with each character that is sent to the printer. This bit is held clear when DMA is not active (CSRA[GO] = 0).<\p> This bit toggles when DMA is active and a character is sent to the printer.
14	-	R	Reserved Writes ignored. Always read as 0.<\p>
13	NRDY	R	Printer Not Ready This bit is negated when: Power and DC voltage are up, and All interlocks are closed, and Paper has been loaded, and No printer faults are present, and The alarm indicator is off. This is not implemented. The printer is always ready and this bit is always read as zero.<\p> Writes are ignored.
12	DPAR	R	LPT Data Parity This bit reflects the printer data parity as sent to the printer. The printer expects odd parity; therefore, if the data has an even number of bits set to ‘1’, the parity (reflected in the CSRB[DPAR] bit) will be ‘1’ The parity is inverted in LPT Parity Test Mode (CSRB[TEST] == 5). This is used to test the parity.<\p> Writes ignored.
11	OVFU	R	Optical Vertical Format Unit This OVFU bit is asserted when an Optical Vertical Format Unit is installed. This bit reflects the LPCCR[OVFU] configuration parameter of the LP20 Console Control Register (LPCCR).<\p>
10-8	TEST	R/W	Test Mode When the LP20 is configured to be in Test Mode (CSRA[MODE] == 1), these bits control which test is to be performed.
			0	Normal operation
			1	DEM Time Test
			2	MSYN Time Test
			3	RAM Parity Test
			4	Memory Parity Test
			5	LPT Parity Test
			6	Page Counter Test
			7	Not used Does nothing
7	OFFLINE	R	Offline This bit reflects the negation of the Online status (CSRA[ONLINE]). Refer there for a description of this bit.
6	VFUE	R	DAVFU Error This is the negation of the Direct Access Vertical Format Unit (DAVFU) Ready (CSRA[VFURDY]). Refer there for a description of this bit.
5	LPE	R	Line Printer Parity Error This bit would normally indicate parity error when transferring data to the line printer. Line printer parity is not implemented in the KS10 FPGA however this is implemented as required to pass the diagnostic tests. This bit is set when: The controller is in LPT Parity Test Mode (CSRB[TEST] = 5), and DMA Data is written to the printer, and Parity Test is enabled (CSRA[PAR] = 1) This bit is cleared when: Parity Test is disabled (CSRA[PAR] = 0) or The controller is no longer in LPT Parity Test Mode (CSRB[TEST] !=5 ) and DMA Data is written to the printer Writes are ignored. Issuing an IO Bridge Clear (UBACSR[INI] = 1), Controller Clear (CSRA[INIT] = 1), or Error Clear (CSRA[ECLR] = 1) does not clear LPE.
4	MPE	R	Memory Parity Error This bit would normally indicate a memory parity error during a DMA operation. Memory parity is not implemented in the KS10 FPGA but this is implemented as required to pass the diagnostic tests. This bit is set when: Parity Tests are enabled (CSRA[PAR] = 1), and The Mode is set to Load RAM Mode (CSRA[MODE] = 3), and The Selected Test is Memory Parity Test (CSRB[TEST] = 4), and A DMA cycle is issued (CSRA[GO] = 1) which accesses memory. This bit is cleared when: Issuing an IO Bridge Clear (UBACSR[INI] = 1), or Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an Error Clear (CSRA[ECLR] = 1).
3	RPE	R	RAM Parity Error This bit indicates a parity failure of the Translation RAM. The parity stored in the Translation RAM is inverted by setting the Test Mode to RAM Parity (CSRB[TEST] = 3). Similarly, the parity read from the Translation RAM is inverted by setting the Test Mode to RAM Parity (CSRB[TEST] = 3). Errors only occur when the data is written and read with a different state of the RAM Parity Test Mode. This bit is set by: Parity Test are enabled (CSRA[PAR] = 1) , and Not in Load DAVFU Mode (CSRA[MODE] != 2), and Enabling Parity Test (CSRA[PAR] = 1) , and Reading RAM data which was stored with inverted parity. This occurs when the data is written with the RAM Test mode in one state and is read with the RAM Test mode in the other state. This bit is cleared by: Issuing an IO Bridge Clear (UBACSR[INI] = 1), or Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an Error Clear (CSRA[ECLR] = 1). Writes are ignored.
2	MSYN	R	IO Bus Time-out Error This bit is set if the LP20 issues a bus request that is not acknowledged. This bit is set by: Enabling Parity Test (CSRA[PAR] = 1) , and Enabling Test Mode (CSRA[MODE] = 2), and Setting the Test to MSYN Time Test (CSRB[TEST] = 2), and Issuing a DMA operation (CSRA[GO] = 1) This bit is cleared by: Issuing an IO Bridge Clear (UBACSR[INI] = 1), or Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an Error Clear (CSRA[ECLR] = 1). Writes are ignored.
1	DTE	R	Demand Timeout Error This bit would normally indicate a handshaking timeout issue between the LP20 and the printer. This interface is not implemented in the KS10 FPGA. This bit is set by: Enabling Test Mode (CSRA[MODE] = 2), and Setting the Test to Demand Time Test (CSRB[TEST] = 1) This bit is cleared by: Issuing an IO Bridge Clear (UBACSR[INI] = 1), or Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an Error Clear (CSRA[ECLR] = 1). Writes are ignored.
0	GOE	R	GO Error This bit is set when an Composite Error (CSRA[ERR]) is present and a GO Command (CSRA[GO]) is issued. This bit is cleared by: Issuing an IO Bridge Clear (UBACSR[INI] = 1), or Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an Error Clear (CSRA[ECLR] = 1). The Go Error Indication is read-only.
0	GOE	W	Page Decrement This is unrelated to the Go Error status described above: when the LP20 is in Page Counter Test Mode ((CSRA[MODE] = 1) and (CSRB[TEST] = 6)), asserting this bit will decrement the Page Counter in the Page Count Register. This magic test mode is write-only.

Bus Address Register (BAR)

The Bus Address Register provides the virtual address of the DMA data. This virtual address is translated to a physical address by the IO Bus Bridge (UBA).

The Bus Address Register is word addressable only.

Bus Address Register (BAR)

Bus Address Register (BAR) – IO Address 775404
Bit(s)	Mnemonic	R/W	Description
15:0	ADDR	R/W	Bus Address This register is modified by a program write. This register is incremented in DMA mode after DMA transaction.<\p> This register is cleared by: Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an IO Bridge Clear (UBACSR[INI] = 1).

Byte Count Register (BCTR)

The Byte Count Register controls the length of a DMA operation. The twos-complement of the number of bytes to load is written into the BCTR. Each DMA cycle increments the BCTR. When the BCTR increments to zero, the DMA operation is complete.

The Byte Count Register is word addressable only.

Byte Count Register (BCTR)

Byte Count Register (BCTR) – IO Address 775406
Bit(s)	Mnemonic	R/W	Description
15:12	-	R	Reserved
11:0	COUNT	R/W	Byte Counter

Page Count Register (PCTR)

The Page Count is loaded with a prescribed number of pages – presumably the number of pages in a box of fan-fold paper. As each page is printed, the PCTR is decremented. When the PCTR is decremented to zero, the Page Count Zero (CSRA[PCZ]) bit is asserted and an interrupt is generated. Again, presumably to wake up the operator and change the paper.

Page Count Register (PCTR)

The Page Count Register is word addressable only.

Page Count Register (PCTR) – IO Address 775410
Bit(s)	Mnemonic	R/W	Description
15:12	-	R	Reserved
11:0	COUNT	R/W	Page Counter

RAM Data Register (RAMD)

Data characters for the Translation RAM are written to the RAM Data Register.

The RAM Data Register is word addressable only.

The RAM Address Register is modified under the following conditions:

Cleared by issuing a Go Command (CSRA[GO] = 1) in Load RAM Mode (CSRA[MODE] = 3)
Cleared by issuing a Controller Clear (CSRA[INIT] = 1), or
Cleared by issuing an IO Bridge Clear (UBACSR[INI] = 1), or
Modified by a write to the CBUF register, or
Modified by a DMA write in Print Mode (CSRA[MODE] = 0), or
Modified by a DMA write in Test Mode (CSRA[MODE] = 1), or
Incremented in Load RAM Mode (CSRA[MODE] = 3) after each DMA transaction.

RAM Data Register (RAMD)

RAM Data Register (RAMD) – IO Address 775412
Bit(s)	Mnemonic	R/W	Description
15:13	-	R	Reserved
12	RAP	R/W	RAM Parity
11	INT	R/W	Interrupt Bit When asserted, causes the controller to generate an interrupt to the processor instead of generating a data strobe to the line printer.
10	DEL	R/W	Delimiter Bit When asserted causes the current and next printer data characters to be taken from the Translation RAM (RAMD) instead of the character buffer (CBUF).
9	TRAN	R/W	Translate Bit When asserted causes the character in RAM be sent to the printer otherwise the character in the character buffer is sent to the printer.
8	PI	R/W	Paper Instruction Bit When asserted causes the printer to interpret the character as a carriage control character rather than data to be printed.
7:0	DATA	R/W	RAM Data The RAM Data Register is written under the following conditions: Program write to the RAMD register, or DMA read in Load RAM Mode (CSRA[MODE] = 3)

Column Counter Register (CCTR) / Character Buffer Register (CBUF)

The column counter is normally used by the DEC LP20 to implement tab characters. When a tab character is found, the LP20 replaces the tab character with a sequence of 1 to 8 spaces. Similarly, the LP20 also causes the printer to wrap text to the next line after column 132.

The Column Counter Register and Character Buffer Register are byte addressable.

Column Counter Register (CCTR) / Character Buffer Register (CBUF)

CCTR and CBUF Register Column Counter Register (CCTR) – IO Address 775414 Character Buffer Register (CBUF) – IO Address 775415
Bit(s)	Mnemonic	R/W	Description
15:8	CCTR	R/W	Column Counter This register is altered when loading Translation RAM via DMA.
7:0	CBUF	R/W	Character Buffer This register is modified by a program write. This register is modified by DMA as follows: DMA write in Print Mode (CSRA[MODE] = 0), or DMA write in Test Mode (CSRA[MODE] = 1), or DMA write in Load DVFU Mode (CSRA[MODE] = 2). This register is cleared by: Issuing a Controller Clear (CSRA[INIT] = 1), or Issuing an IO Bridge Clear (UBACSR[INI] = 1).

Checksum Register (CKSM) / Printer Data Register (PDAT)

The Checksum Register is used to verify the integrity of DMA transfers. The Checksum Register is set to zero when the DMA operation starts and the register accumulates the data bytes during the DMA operation. When the DMA operation has completed, the checksum is reported in this register.

The Checksum Register and Printer Data Register are byte addressable.

Printer Data Register (PDAT) / Checksum Register (CKSM)

PDAT and CKSM Register Printer Data Register (PDAT) – IO Address 775416 Checksum Register (CKSM) – IO Address 775417
Bit(s)	Mnemonic	R/W	Description
15:8	CKSM	R	Checksum
7:0	PDAT	R	Printer Data

LP20 Interrupts

LP20 Modes

The LP20 has four major modes: Print Mode, Test Mode, Load DAVFU Mode, and Load RAM Mode. These modes are described in the following sections.

Print Mode

The Print Mode is the normal mode of operation.

Test Mode

In Test Mode, the print characters are not printed and the printer handshake lines are looped back to the LP20. This mode behaves as-if the printer output was routed to the bit-bucket – even if a printer is not present. Optionally other hardware tests are enabled for hardware testing.

These optional tests are described in the following sections.

Normal Test Mode

In Normal Test Mode, no additional test modes are enabled. As stated above, nothing is output to the printer.

Demand Timeout Test Mode

The Demand Timeout Test Mode disables the handshake acknowledge from the printer. This causes the printer interface to timeout and assert a Demand Timeout Error (CSRB[DTE]).

In the KS10 FPGA, the Demand Timeout Error is asserted while the unit is in Demand Timeout Test Mode.

SSYN Timeout Test Mode

The SSYN Timeout Test Mode disables the DMA acknowledge from the memory subsystem. This will cause the DMA controller to timeout and assert a IO Bus Time-out Error (CSRB[MSYN]).

RAM Parity Test Mode

In RAM Parity Test Mode, the parity written to the RAM and the parity read from RAM are inverted.

A RAM parity error will occur if the RAM is written with the RAM Parity Test Mode in one state and the RAM is read with the RAM Parity Test Mode in other state.

Memory Parity Test Mode

Memory parity is not implemented. In Memory Parity Test Mode, every DMA access of memory will generate a Memory Parity Error (CSRB[MPE]).

Line Printer Parity Test Mode

Line printer parity is not implemented. In Line Printer Parity Test Mode, every printed character will generate a Line Printer Parity Error (CSRB[LPE]).

Page Counter Test Mode

The Page Counter Test Mode allows the Page Counter hardware to be tested and is enabled by setting the controller into Test Mode (set CSRA[MODE[2:0]] = 2) and selecting the Page Counter Test Mode (CSRB[TEST[2:0]]) = 6).

In this mode, Page Counter is incremented every time a ‘1’ written to the Go Error bit in the CSRB (CRSB[GOE] = 1).

Load DAVFU Mode

The Load DAVFU Mode allows the DAVFU to be updated via DMA.

Load Translation RAM Mode

The Load RAM Mode allows the Translation RAM to be updated via DMA.

DSLPA Transcript

A transcript of the Line Printer Diagnostic Tests is included below:

SMMON CMD - DSLPA

DECSYSTEM 2020 LINE PRINTER DIAGNOSTIC [DSLPA]
VERSION 0.7, SV=0.3, CPU#=4097, MCV=130, MCO=470, HO=0, KASW=003740 000000

TTY SWITCH CONTROL ? - 0,S OR Y  - Y

LH SWITCHES <# OR ?> - 0
RH SWITCHES <# OR ?> - 40
SWITCHES = 000000 000040

IS THIS AN LP05, LP14 OR LP26 LINE PRINTER ? Y OR N  - Y

DOES THIS LPT HAVE A DAVFU ? Y OR N  - Y

TYPE ? TO GET FORMAT ON TERMINAL,
TYPE # TO GET FORMAT PRINTED ON THE LPT
COMMANDS: XX OR XX-YY OR A OR D

*A
STARTING *BASIC REGISTER TESTING*
STARTING *REGISTER DISTURB TESTING*
STARTING *RAM ADDRESS AND DATA TESTING*
STARTING *SPECIAL PURPOSE REGISTER TESTING*
STARTING *(RAM)NPR TESTING*
STARTING *TEST MODE LOGIC TESTING*
STARTING *BASIC INTERRUPT TESTING*
STARTING *MISC LOGIC TESTING*
STARTING *ADVANCED DAVFU TESTING*
CHANNEL-PASS NUMBER: (1-16, CR=ALL CHANNELS)
LPT WENT OFF LINE CORRECTLY - PLEASE RESET.
LPT IS NOW ON LINE!
LPT WENT OFF LINE CORRECTLY - PLEASE RESET.
LPT IS NOW ON LINE!
CHANNEL NUMBER: (1-12, CR=ALL CHANNELS)
TESTING CHANNEL NUMBER 1
LPT WENT OFF LINE CORRECTLY - PLEASE RESET.
LPT IS NOW ON LINE!
TESTING CHANNEL NUMBER 2
LPT WENT OFF LINE CORRECTLY - PLEASE RESET.
LPT IS NOW ON LINE!
TESTING CHANNEL NUMBER 3
LPT WENT OFF LINE CORRECTLY - PLEASE RESET.
LPT IS NOW ON LINE!
TESTING CHANNEL NUMBER 4
LPT WENT OFF LINE CORRECTLY - PLEASE RESET.
LPT IS NOW ON LINE!
TESTING CHANNEL NUMBER 5
LPT WENT OFF LINE CORRECTLY - PLEASE RESET.
LPT IS NOW ON LINE!
TESTING CHANNEL NUMBER 6
LPT WENT OFF LINE CORRECTLY - PLEASE RESET.
LPT IS NOW ON LINE!
TESTING CHANNEL NUMBER 7
LPT WENT OFF LINE CORRECTLY - PLEASE RESET.
LPT IS NOW ON LINE!
TESTING CHANNEL NUMBER 8
LPT WENT OFF LINE CORRECTLY - PLEASE RESET.
LPT IS NOW ON LINE!
TESTING CHANNEL NUMBER 9
LPT WENT OFF LINE CORRECTLY - PLEASE RESET.
LPT IS NOW ON LINE!
TESTING CHANNEL NUMBER 10
LPT WENT OFF LINE CORRECTLY - PLEASE RESET.
LPT IS NOW ON LINE!
TESTING CHANNEL NUMBER 11
LPT WENT OFF LINE CORRECTLY - PLEASE RESET.
LPT IS NOW ON LINE!
TESTING CHANNEL NUMBER 12
LPT WENT OFF LINE CORRECTLY - PLEASE RESET.
LPT IS NOW ON LINE!
STARTING *LP20 PATTERN PRINTING TESTS*
TEST 122: EVERY COLUMN PRINTS THE SAME CHARACTER
TEST 123: MODIFIED RIPPLE PATTERN
TEST 124: VERTICAL ALIGNMENT PATTERN
TEST 125: HORIZONTAL ALIGNMENT PATTERN
TEST 126: CHECK HORIZONTAL TABS
TEST 127: CHECK THE OVERFLOW CORRECTION LOGIC
TEST 130: COMPLEMENT PATTERN (" " AND "_")
TEST 131: COMPLEMENT PATTERN ("*" AND "U")
TEST 132: COMPLEMENT PATTERN ("RUBOUT" AND "NULL")
TEST 133: CARRIAGE RETURN WITHOUT LINEFEED
TEST 134: EXERCISE COLUMN COUNTER
TEST 135: ILLEGAL CHARACTERS (EXEC MODE ONLY)
TEST 136: EXERCISE COLUMN COUNTER
TEST 137: CHARACTER SPACING TEST
TEST 140: OVERPRINT TEST
TEST 141: DC0-4 TEST
TEST 142: DC3 TEST
TEST 143: DC1 TEST
TEST 144: DC2 TEST
TEST 145: DC4 TEST
TEST 146: DC0 TEST
TEST 147: VT TEST
TEST 150: PRINT SPEED TEST (EXEC MODE ONLY)
CHARACTER PRINT RATE = 2984 LINES PER MINUTE.
TEST 151: CARRIAGE RETURN WITHOUT LINEFEED (SHUTTLE TEST #2)
TEST 152: EXERCISES COLUMN COUNTER (PATTERN #2)
TEST 153: SWIRL TEST PATTERN

*L
TEST#           FUNCTION                TEST#           FUNCTION
-----           --------                -----           --------
 1      LP20 REGISTER ACCESS TEST        2      CSRA REGISTER R/W TEST
 3      CSRA HI-BYTE TEST                4      CSRA LO-BYTE TEST
 5      CSRA CLR TEST (LOINIT)           6      CSRA CLR TEST (UBINIT)
 7      CSRB REGISTER R/W TEST           10     CSRB HI-BYTE TEST
 11     CSRB LO-BYTE TEST                12     CSRB CLR TEST (LOINIT)
 13     CSRB CLR TEST (UBINIT)           14     BUSADR REGISTER R/W TEST
 15     BUSADR CLR TEST (LOINIT)         16     BUSADR CLR TEST (UBINIT)
 17     BYTCNT REGISTER R/W TEST         20     BYTCNT CLR TEST (LOINIT)
 21     BYTCNT CLR TEST (UBINIT)         22     PGCNTR REGISTER R/W TEST
 23     PGCNTR CLR TEST (LOINIT)         24     PGCNTR CLR TEST (UBINIT)
 25     RAMDAT REGISTER R/W TEST         26     CHARBF REGISTER R/W TEST
 27     CHARBF CLR TEST (LOINIT)         30     CHARBF CLR TEST (UBINIT)
 31     CHARBF LO-BYTE TEST              32     CHARBF HI-BYTE TEST
 33     PNTDAT HI-BYTE ADR TEST          34     PNTDAT LO-BYTE ADR TEST
 35     CSRA 0'S DISTURB TEST            36     CSRB 0'S DISTURB TEST
 37     BUSADR 0'S DISTURB TEST          40     BYTCNT 0'S DISTURB TEST
 41     PGCNTR 0'S DISTURB TEST          42     RAMDAT 0'S DISTURB TEST
 43     COLCNT 0'S DISTURB TEST          44     PNTDAT 0'S DISTURB TEST
 45     (RAM) BASIC ADR TEST             46     (RAM)BASIC PAR NET TEST (PR=1)
 47     (RAM)BASIC PAR NET TEST (PR=0)   50     (RAM) BASIC COMPLIMENT ADR TEST
 51     (RAM)FLOATING 1'S & 0'1 ADR TEST 52     (RAM)0'S & 1'S DISTURB TEST
 53     (RAM) PAR GEN NET TEST           54     (RAM) PAR GEN NET TEST (RAMTST)
 55     (RAM) DISABLE LOAD TEST          56     (RAM) DISABLE READ TEST
 57     PGCNTR DECREMENT TEST            60     PGCNTR DECREMENT CARRY TEST
 61     PGCNTR (GOERR)DECREMENT TEST     62     PGCNTR (PAGTST)DECREMENT TEST
 63     (RAM) 1 WORD NPR XFER TEST       64     (RAM) BASIC NPR DATA XFER TEST
 65     (RAM) SSYN TIMEOUT(SYNTIM)TEST   66     (RAM) SSYN TIMEOUT(ERROR)TEST
 67     DEMAND TEST (DEMTIM)             70     DEMAND TEST (LOINIT)
 71     DEMAND TEST (ERROR)              72     MEMTST TEST (MEMPAR)
 73     MEMTST TEST CLEAR (LOINIT)       74     MEMTST TEST (ERROR)
 75     GO ERROR TEST SET (GOERR)        76     GO ERROR CLEAR (GOERR)
 77     BASIC INTERRUPT TEST             100    DAVFU BASIC INTERRUPT TEST
 101    LPC9 SEL BYTE CNTR (CLR DONE)    102    LPR2 BYTE CNTR ZERO (SET DONE)
 103    LPD4 PAGE CNTR EMPTY (SET PAGZRO)104    LP8C CLR 1 L (CLEAR PAGE ZERO)
 105    LPC9 SEL PAGE CNTR L (CLR PAGZRO)106    CHECKSUM LOGIC TEST
 107    LINE-PRINTER PARITY TEST         110    DAVFU FORMAT MEMORY BIT
 111    DAVFU FORMAT MEMORY ADDRESS TEST 112    DAVFU OVERFLOW TEST
 113    DAVFU ODD NUMBER TEST            114    DAVFU NO STOPS TEST
 115    DAVFU OVERPRINT TIME-OUT TEST    116    DAVFU 8 LPI FORCE TEST
 117    DAVFU 6 LPI FORCE TEST           120    DELIMITER HOLD TEST

***************** PATTERN PRINTING TESTS *******************

 122    EVERY COLUMN                     123    MODIFIED RIPPLE PATTERN
 124    VERTICAL ALIGNMENT               125    HORIZONTAL ALIGNMENT
 126    HORIZONTAL TABS                  127    OVERFLOW CORRECTION
 130    COMPLEMENT " " AND "-"           131    COMPLEMENT "*" AND "U"
 132    COMPLEMENT "RUBOUT" AND "NULL"   133    SHUTTLE TEST #1
 134    COLUMN COUNTER (INCREASING)      135    ILLEGAL CHARACTERS (EXEC MODE)
 136    COLUMN COUNTER (DECREASING)      137    CHARACTER SPACING
 140    OVERPRINT TEST                   141    DC0 - DC4
 142    DC3 TEST                         143    DC1 TEST
 144    DC2 TEST                         145    DC4 TEST
 146    DC0 TEST                         147    VT TEST
 150    SPEED TEST (EXEC MODE ONLY)      151    SHUTTLE TEST #2
 152    COLUMN COUNTER (SPECIAL)         153    SWIRL PATTERN

*

FPGA Status

The LP20 Printer Controller and the LP26 printer emulation is stable with no known deficiencies. While the KS10 system supported printers other than the LP26, only the LP26 printer emulation is provided. The DSLPA diagnostics has provisions for testing an LP07 printer which will fail as expected because the LP07 and LP26 behave differently in some cases.

                           DIAGNOSTIC                              Result
------------------------------------------------------------------ ------
DSLPA DECSYSTEM 2020 LINE PRINTER DIAGNOSTIC [DSLPA]               Pass

LP20 Printer Controller - KS10FPGA/KS10FPGA GitHub Wiki

LP20 Registers

Control/Status A Register (CSRA)

Control/Status B Register (CSRB)

Bus Address Register (BAR)

Byte Count Register (BCTR)

Page Count Register (PCTR)

RAM Data Register (RAMD)

Column Counter Register (CCTR) / Character Buffer Register (CBUF)

Checksum Register (CKSM) / Printer Data Register (PDAT)

LP20 Interrupts

LP20 Modes

Print Mode

Test Mode

Normal Test Mode

Demand Timeout Test Mode

SSYN Timeout Test Mode

RAM Parity Test Mode

Memory Parity Test Mode

Line Printer Parity Test Mode

Page Counter Test Mode

Load DAVFU Mode

Load Translation RAM Mode

DSLPA Transcript

FPGA Status

⚠️ GitHub.com Fallback ⚠️

LP20 Printer Controller - KS10FPGA/KS10FPGA GitHub Wiki

LP20 Registers

Control/Status A Register (CSRA)

Control/Status B Register (CSRB)

Bus Address Register (BAR)

Byte Count Register (BCTR)

Page Count Register (PCTR)

RAM Data Register (RAMD)

Column Counter Register (CCTR) / Character Buffer Register (CBUF)

Checksum Register (CKSM) / Printer Data Register (PDAT)

LP20 Interrupts

LP20 Modes

Print Mode

Test Mode

Normal Test Mode

Demand Timeout Test Mode

SSYN Timeout Test Mode

RAM Parity Test Mode

Memory Parity Test Mode

Line Printer Parity Test Mode

Page Counter Test Mode

Load DAVFU Mode

Load Translation RAM Mode

DSLPA Transcript

FPGA Status

⚠️ **GitHub.com Fallback** ⚠️

⚠️ GitHub.com Fallback ⚠️