KS10 FPGA - KS10FPGA/KS10FPGA GitHub Wiki

The KS10 FPGA Block Diagram

The KS10 FPGA consists of the KS10 CPU, Memory Subsystem, Console Subsystem, and some IO Bus Bridges.

IO Bus Bridge #1 supports a single RH-11 Massbus Controller attached to 8x RP06 Disk Drives. This interface was generally limited to this single peripheral because of Unibus performance issues.

IO Bus Bridge #2 was not originally implementable because of KS10 backplane design limitation. This could be fixed in the KS10 FPGA, but no software would support it.

IO Bus Bridge #3 supports the bulk of the peripherals including a RH11 Massbus Controller attached to 8x TM03/TU77 Tape Drives, a DZ-11 8-Port Terminal Multiplexer, a LP20 Line Printer Controller, a DUP11 Communications Controller, and a KMC11 General Purpose Microcontroller.

IO Bus Bridge #4 supports 4x Unibus Exercisers which are used to test the IO Bridge (UBA) implementation.

Note: UBA1, UBA3, and UBA4 are testable by the DSUBA diagnostic.

The block diagram of the KS10 FPGA System is illustrated below:

Each of the major blocks has an independent wiki page which describes its operation.