KMC11 General Purpose Microprocessor - KS10FPGA/KS10FPGA GitHub Wiki

The KMC11 is a communications co-processor that is used to off-load DUP11 data movement tasks from the KS10 to the KMC11.

The KS10 only supports a single KMC11; however, a single KMC11 can manage several DUP11 Synchronous Serial Interfaces.

The KMC11 Verilog implementation is fully parameterized: the base IO address and the interrupt vector are controlled by module parameters.

It should be noted that there are two somewhat incompatible versions of the KMC11: the KMC11A and the KMC11B. There is a programming manual for the KMC11A and a set of Engineering prints for the KMC11B. The KS10 diagnostics support the KMC11A.

Between the two sets of documents and the DSKMA diagnostics, you can reverse engineer many of the implementation details.

These documents are available for download from:

KMC11 Programmers Manual (AA-5244-TC)
KMC11B Field Maintenance Print Set (KMC11-B-1)

The KMC11A and the KMC11B are incompatible as follows:

  • The microcode loading procedure is completely different. On the KMC11A you must load the address and the load the instruction for each instruction. On the KMC11B the address will auto-increment after you load an instruction. This significantly reduces the time to load microcode.
  • The KMC11A supports 1K words of microcode while the KMC11B supports 4K words of microcode.
  • The KMC11A supports 1K bytes of data memory while the KMC11B supports 4K bytes of data memory.
  • The KMC11B has additional status registers that can be read at upper INBUS* addresses.

Note: Only the KMC11A is supported by the KS10 diagnostics and by TOPS-10 and that is what is implemented.

The KMC11 configuration is illustrated below:

KMC11 Configuration

Device

UBA

Interrupt

Interrupt
Vector

Base
Address

KMC11 #1

UBA 3

5

000540
000544

760540

KMC11 Interface Registers

These registers are visible to the KS10 processor

A summary of KMC11 interface registers is summarized below:

KMC11 Register Summary

IO Addr

Register
Name

Access

Register Description

760540

CSR0

Byte (R/W)

Control and Status Register #0

760541

CSR1

Byte (R/W)

Control and Status Register #1

760542

CSR2

Byte (R/W)

Control and Status Register #2

760543

CSR3

Byte (R/W)

Control and Status Register #3

760544

CSR4

Byte (R/W)

Control and Status Register #4

760545

CSR5

Byte (R/W)

Control and Status Register #5

760546

CSR6

Byte (R/W)

Control and Status Register #6

760547

CSR7

Byte (R/W)

Control and Status Register #7

KMC11 Control and Status Registers

The KMC11 Control and Status Registers are general purpose registers used for communications between the KS10 and the KMC11. These registers are implemented using multi-port memory so that they can be accessed by the KS10 and by the KMC11.

These registers have no pre-defined purpose and can be used for anything.

These registers are shadowed by a set of Maintenance Registers: specifically the Maintenance Register, the Maintenance Address Register, and the Maintenance Instruction Register. In general, these register are used for loading, controlling, and executing KMC11 microcode.

These registers are read/write and are byte addressable.

These registers are illustrated below.

KMC11 Register Set

KMC11 Maintenance Register

The Maintenance Register is used for loading and controlling the operation of the KMC11.

The Maintenance Register shadows the CSR1 register which exists in multi-port memory. Writes to that Unibus IO address go to both the Maintenance Register and to the CSR1 register in multi-port memory. Unibus IO reads return the value of the Maintenance Register - not CSR1.

That implies that the KMC11 can observe the state of Maintenance Register. The KMC11 can modify the value of the value of CSR1 in the multi-port memory, but it cannot alter the state of the Maintenance Register.

KMC11 Maintenance Register (MAINT) – IO Address 760541

Bit(s)

Mnemonic

R/W

Description

15

RUN

R/W

RUN

When RUN is asserted, this causes the KMC11 to execute instructions.

This bit is asserted by writing a 1.

This bit is negated by:

  1. Writing a 0, or
  2. Asserting KMC11 Master Clear (CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

14

MCLR

W

Master Clear

Asserting Master Clear has the following effect:

  1. Effects the bits in the Maintenance Register as follows:
    1. Resets RUN, and
    2. Resets MCLR, and
    3. Resets CRAMWR, and
    4. Resets LUSTEP, and
    5. Resets LULOOP, and
    6. Resets CRAMOUT, and
    7. Resets CRAMIN, and
    8. Resets STEP.
  2. Effects the bits in the MISC register as follows:
    1. Resets VECTXXX4, and
    2. Resets LAT, and
    3. Sets PGMCLK, and
    4. Resets BAI[17:16], and
    5. Resets ACLO, and
    6. Resets NXM, and
  3. Effects the bits in the NPR register as follows:
    1. BYTEXFER
    2. NPRO
    3. BAEI[17:16]
    4. NLXFER
    5. NPRRQ
  4. Resets the ALU Zero-bit (Z), and
  5. Resets the ALU Carry-bit (C), and
  6. Resets the Branch Register (BRG), and
  7. Resets the Memory Address Register (MAR), and
  8. Resets the Program Counter (PC), and
  9. Resets the Maintenance Address Register, and
  10. Resets the Maintenance Instruction Register, and
  11. Resets all timing signals.

Asserting Master Clear does not alter the following:

  1. The contents of the Multiport Memory, or
  2. The Control RAM (CRAM), or
  3. The Data Memory (MEM), or
  4. The scratchpad memory (SPR), or
  5. The state associated with NPR Requests, or
  6. The state associated with Interrupt Requests.

MCLR is always read as zero.

13

CRAMWR

W

CRAM Write

This bit is used to write microcode into the Control RAM (CRAM).

When CRAM Write CSR1[CRAMW] is asserted and CSR1[ROMOUT] is asserted, the contents of Maintenance Instruction Register is loaded into the CRAM at the address specified by Maintenance Address Register.

CRAMWR is always read as zero.

12

LUSTEP

R/W

Line Unit Step

Asserted by writing a '1'.

Negated by:

  1. Writing a 0, or
  2. Asserting KMC11 Master Clear (CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

11

LULOOP

R/W

Line Unit Loopback

Negated by:

  1. Writing a 0, or
  2. Asserting KMC11 Master Clear (CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

10

CRAMOUT

R/W

CRAM Output

When CRAM Output is negated:

  • Reads from SEL 4 return the contents of CSR4/5.
  • Reads from SEL 6 return the contents of CSR6/7.
  • The NPROD Register provides the data for an NPR output operation.

When CRAM Output is asserted:

  • Reads from SEL 4 return the contents of the Maintenance Address Register.
  • Reads from SEL 6 return the contents of the Maintenance Instruction Register.
  • The Maintenance Address Register provides the data for an NPR output operation.

This bit is asserted by writing a 1.

This bit is negated by:

  1. Writing a 0, or
  2. Asserting KMC11 Master Clear (CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

9

CRAMIN

R/W

CRAM Input

When CRAM Input is negated, single-stepped instructions execute the contents of the CRAM at the address pointed-to by the MAR.

When CRAM Input is asserted, single-stepped instructions execute the contents of the Maintenance Instruction Register.

This bit is asserted by writing a 1.

This bit is negated by:

  1. Writing a 0, or
  2. Asserting KMC11 Master Clear (CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

Once the Maintenance Instruction Register is loaded, it can either be stored into the CRAM by asserting CRAM Write or executed by asserting STEP.

8

STEP

W

Single Step Microprocessor

When asserted, this bit steps the microprocessor through one instruction cycle.

Note: The RUN bit should be negated before executing this control function.

This bit is always read as zero.

The microcode is loaded into the KMC11 using the following procedure:

  1. Assert only the CRAMOUT bit in CSR0, then
  2. Write the CRAM address into Maintenance Address Register (SEL 4), then
  3. Write the microcode instruction into Maintenance Instruction Register (SEL 6), then
  4. Assert CRAMWR (leaving CRAMOUT asserted) in CSR0.
  5. Negate CRAMWR (leaving CRAMOUT asserted) in CSR0.
  6. Repeat for each word of microcode.

The microcode may be verified using the following procedure:

  1. Assert only the CRAMOUT bit in CSR0, then
  2. Write the CRAM address into Maintenance Address Register (SEL 4), then
  3. Read data from the Maintenance Instruction Register (SEL 6), then
  4. Clear CSR0.
  5. Repeat for each word of microcode.

A single microcode instruction may be executed by:

  1. Assert only the CRAMIN bit is CSR0, then
  2. Write the microcode instruction into Maintenance Instruction Register (SEL 6), then
  3. Assert STEP (as well as CRAMIN) in CSR0, then
  4. Negate CRAMIN, CRAMOUT (if asserted), and STEP bits

KMC11 Maintenance Address Register

The Maintenance Address Register is used to load microcode into the KMC11. Specifically, this register provides the address when microcode is written into the KMC11 Control RAM (CRAM).

From the IO Bus (Unibus) perspective, the Maintenance Address Register shadows CSR4 and CSR5. Writes to SEL 4 are directed at both the CSRs and the Maintenance Address Register.

When CSR1[CRAMOUT] is negated, reads to SEL 4 return the contents of CSR4 and CSR5. When CSR1[CRAMOUT] is asserted, reads to SEL 4 return the contents of the Maintenance Address Register.

KMC11 Maintenance Address Register – IO Address 760544

Bit(s)

Mnemonic

R/W

Description

15-12

-

R

Reserved

Writes ignored

Always read as zero.

11-0

ADDR

R/W

Control RAM Address

These bits are set by writing ones.

This bits are cleared by:

  1. Writing zeros, or
  2. Asserting KMC11 Master Clear (CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

KMC11 Maintenance Instruction Register

The Maintenance Instruction Register is used to load microcode into the KMC11. Also, the KMC11 can execute a single instruction placed into this register.

From the IO Bus (Unibus) perspective, the Maintenance Instruction Register shadows CSR6 and CSR7. Writes to SEL6 are directed at both the CSRs and the Maintenance Address Register.

When CSR1[CRAMOUT] is negated, reads to SEL6 return the contents of CSR6 and CSR7. When CSR1[CRAMOUT] is asserted, reads to SEL6 return the contents of the Maintenance Instruction Register.

KMC11 Maintenance Instruction Register – IO Address 760546

Bit(s)

Mnemonic

R/W

Description

15-0

INST

R/W

Instruction

These bits is set by writing a ones.

This bit is cleared by:

  1. Writing zeros, or
  2. Asserting KMC11 Master Clear (CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

KMC11 Microprocessor Registers

The following registers are visible from the KMC11 and may or may not be visible to the KS10 depending on the register.

KMC11 NPR Input Data (NPRID) Register

KMC11 NPR Output Data (NPROD) Register

KMC11 NPR Input Address (NPRIA) Register

KMC11 NPR Output Address (NPROA) Register

KMC11 CSR0 Register

KMC11 CSR1 Register

KMC11 CSR2 Register

KMC11 CSR3 Register

KMC11 CSR4 Register

KMC11 CSR5 Register

KMC11 CSR6 Register

KMC11 CSR7 Register

KMC11 NPR Control Register

The NPR Control Register is an 8-bit register in the KMC11 Microprocessor that performs some basic IO. It is not addressable by the KS10 in any way.

The NPR Control Register is as follows:

KMC11 NPR Control Register (NPRC)

KMC11 NPR Control Register (NPRC)

Bit(s)

Mnemonic

R/W

Description

7

BYTEXFER

R/W

Byte Transfer

When asserted, NPR operations will be byte transfers; otherwise the NPR transfers will be 16-bit or 18-bit word transfers.

This bit is set by writing a 1.

  1. Writing a 0, or
  2. Asserting KMC11 Master Clear (CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

6

MAR[10]

R

MAR[10]

This provides access to the Memory Address Register bit 10.

The KMC11 provides 1K of memory. This bit is set when the memory address increments (overflows) from the top of memory to the bottom of memory.

Writes ignored.

Some documents

5

MAR[8]

R

MAR[8]

This provides access to the Memory Address Register bit 8.

The memory address is segmented into 4x 256 byte pages. This bit is located at the page boundary. This is useful because the address increment can increment the page.

Writes ignored.

4

NPRO

R/W

NPR Out

When NPRO is asserted and NPRQ is asserted, the KMC11 will perform a NPR write operation. When NPRO is negated and NPRQ is asserted, the KMC11 will perform a NPR read operation.

This bit is set by writing a 1.

This bit is cleared by:

  1. Writing a 0, or
  2. Asserting KMC11 Master Clear (CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

3-2

BAEI[17:16]

R/W

Base Address Extension for NPR Reads (Bits 17:16)

These bits provide the upper two bits of the NPR address during NPR read transactions.

These bits are set by writing a ones.

These bits are cleared by:

  1. Writing a zeros, or
  2. Asserting KMC11 Master Clear (CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

1

NLXFER

R/W

Not Last Transfer

This bit allows multiple NPR transactions to occur without renegotiating for access to the KS10 Backplane Bus. This is not implemented. Every NPR access is negotiated.

This bit is set by writing a 1.

This bit is cleared by:

  1. Writing a 0, or
  2. Asserting KMC11 Master Clear (CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

0

NPRRQ

R/W

NPR Request

Asserting this bit will start a single NPR transaction. When the NPR transaction is completed, this bit will automatically clear.

KMC11 MISC Register

The MISC Register is an 8-bit register in the KMC11 Microprocessor that performs some basic IO. It is not addressable by the KS10 in any way.

The MISC Register is as follows:

KMC11 MISC Register (MISC)

KMC11 MISC Register (MISC)

Bit(s)

Mnemonic

R/W

Description

7

IRQO

R/W

Interrupt Request Out

Asserting this bit creates an interrupt request to the KS10.

This bit is set by writing a 1.

This bit is cleared when the interrupt is acknowledged.

6

VECTXXX4

R/W

This selects between the two interrupt vectors. When this bit is asserted, the interrupt vector will be 000544 otherwise the interrupt vector will be 000540.

This bit is set by writing a 1.

This bit is cleared by:

  1. Writing a 0, or
  2. Asserting KMC11 Master Clear(CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBASTAT[INI]).

5

LAT

R/W

Latch

This is just a bit that has no particular purpose

This bit is set by writing a 1.

This bit is cleared by:

  1. Writing a 0, or
  2. Asserting KMC11 Master Clear(CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBASTAT[INI]).

4

PGMCLK

R/W

Retriggerable Timer

This bit triggers a 50 microsecond re-triggerable timer. When triggered, the PGMCLK pin negates and remains negated for 50 microseconds. If the PGMCLK pin is triggered while the timer is active, the timer is reset to 50 microseconds again.

This bit is set when:

  1. The Timer expires, or
  2. Asserting KMC11 Master Clear(CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBASTAT[INI]).

This bit is cleared by asserting this bit when the timer is inactive.

3-2

BA[17:16]

R/W

DMA Read Bus Address 17:16

These bits provide the upper two bits of the DMA address during DMA read transactions.

These bits are set by writing ones.

These bits is cleared by:

  1. Writing zeros, or
  2. Asserting KMC11 Master Clear(CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBASTAT[INI]).

1

ACLO

R/W

When asserted this forces a Power Fail condition to the KS10 CPU. This is not implemented.

This bit is set by writing a 1.

This bit is cleared by:

  1. Writing a 0, or
  2. Asserting KMC11 Master Clear(CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBASTAT[INI]).

0

NXM

R

Non-existent Memory

Although the KS10 FPGA implements all memory, NXM will be asserted when a DMA access causes an IO Bus Bridge Paging Failure.

This bit is asserted when the DMA operation times out waiting for a memory acknowledge.<\p>

This bit is cleared by:

  1. Writing a 0, or
  2. Asserting KMC11 Master Clear(CSR1[MCLR]), or
  3. Asserting IO Bridge Clear (UBASTAT[INI]).

DSKMA Transcript

SMMON CMD - DSKMA

DSKMA DECSYSTEM 2020 KMC11 DIAGNOSTICS
VERSION 0.1, SV=0.3, CPU#=2020, MCV=130, MCO=470, HO=0, KASW=003740 000000

TTY SWITCH CONTROL ? - 0,S OR Y  - 0
SWITCHES = 000000 000000

MEMORY MAP =
FROM     TO          SIZE/K
00000000 03777777       1024


'COMMAND MODE' IS INDICATED WHEN THE PROGRAM
 TYPES AN "*" AT THE LEFT SIDE OF THE TERMINAL. TO RE-START
 FROM 'COMMAND MODE' TYPE "&".
 TYPE ? TO GET FORMAT ON (TERMINAL),
 OR % TO GET SUMMARY OF CONTROLLER TESTS.

*%
TEST.1--*REGISTER ACCESS TEST*
TEST.2--*KMCSR CLEAR TEST*
TEST.3--*REGISTER WRITE/DUAL READ TEST*
TEST.4--*CONTROL STATUS REGISTER WRITE/READ (BIT0) TEST*
TEST.5--*CONTROL STATUS REGISTER WRITE/READ (BIT1) TEST*
TEST.6--*CONTROL STATUS REGISTER WRITE/READ (BIT2) TEST*
TEST.7--*CONTROL STATUS REGISTER WRITE/READ (BIT5) TEST*
TEST.10--*CONTROL STATUS REGISTER WRITE/READ (BIT6) TEST*
TEST.11--*CONTROL STATUS REGISTER WRITE/READ (BIT7) TEST*
TEST.12--*CONTROL STATUS REGISTER WRITE/READ (BIT9) TEST*
TEST.13--*CONTROL STATUS REGISTER WRITE/READ (BIT11) TEST*
TEST.14--*CONTROL STATUS REGISTER WRITE/READ (BIT12) TEST*
TEST.15--*CONTROL OUT REGISTER WRITE/READ (BIT0) TEST*
TEST.16--*CONTROL OUT REGISTER WRITE/READ (BIT1) TEST*
TEST.17--*CONTROL OUT REGISTER WRITE/READ (BIT2) TEST*
TEST.20--*CONTROL OUT REGISTER WRITE/READ (BIT6) TEST*
TEST.21--*CONTROL OUT REGISTER WRITE/READ (BIT7) TEST*
TEST.22--*CONTROL OUT REGISTER WRITE/READ (BIT12) TEST*
TEST.23--*CONTROL OUT REGISTER WRITE/READ (BIT13) TEST*
TEST.24--*PORT4 FLOATING BITS TEST*
TEST.25--*PORT6 FLOATING BITS TEST*
TEST.26--*CONTROL STATUS REGISTERS BYTE ADDRESSING WRITE/DUAL READ TEST*
TEST.27--*MAINTENANCE INSTRUCTION REGISTER UBACLR TEST*
TEST.30--*MAINTENANCE INSTRUCTION REGISTER MSTCLR TEST*
TEST.31--*MICRO-PROCESSOR TEST*
TEST.32--*MICRO PROCESSOR IBUS* REGISTER 0 WRITE/READ TEST*
TEST.33--*MICRO PROCESSOR IBUS* REGISTER 2 WRITE/READ TEST*
TEST.34--*MICRO PROCESSOR IBUS* REGISTER 4 WRITE/READ TEST*
TEST.35--*MICRO PROCESSOR IBUS* REGISTER 5 WRITE/READ TEST*
TEST.36--*MICRO PROCESSOR IBUS* REGISTER 10 WRITE/READ TEST*
TEST.37--*MICRO PROCESSOR IBUS* REGISTER 11 WRITE/READ TEST*
TEST.40--*MICRO PROCESSOR IBUS REGISTER 0 WRITE/READ TEST*
TEST.41--*MICRO PROCESSOR IBUS REGISTER 1 WRITE/READ TEST*
TEST.42--*MICRO PROCESSOR IBUS REGISTER 2 WRITE/READ TEST*
TEST.43--*MICRO PROCESSOR IBUS REGISTER 3 WRITE/READ TEST*
TEST.44--*MICRO PROCESSOR IBUS REGISTER 4 WRITE/READ TEST*
TEST.45--*MICRO PROCESSOR IBUS REGISTER 5 WRITE/READ TEST*
TEST.46--*MICRO PROCESSOR IBUS REGISTER 6 WRITE/READ TEST*
TEST.47--*MICRO PROCESSOR IBUS REGISTER 7 WRITE/READ TEST*
TEST.50--*MICRO PROCESSOR IBUS DUAL ADDRESS TEST*
TEST.51--*MICRO PROCESSOR BR REGISTER WRITE/READ TEST*
TEST.52--*SCRATCH PAD WRITE/READ TEST*
TEST.53--*SCRATCH PAD DUAL ADDRESSING TEST*
TEST.54--*VECTOR A INTERRUPT TEST*
TEST.55--*VECTOR B INTERRUPT TEST*
TEST.56--*HI PRIORITY INTERRUPT TEST*
TEST.57--*LOW PRIORITY INTERRUPT TEST*
TEST.60--*DATO NPR TEST*
TEST.61--*DATI NPR TEST*
TEST.62--*DATOB NPR TEST*
TEST.63--*DATIB NPR TEST*
TEST.64--*RANDOM MEM NPR TEST*
TEST.65--*DATO TEST OF EA BITS 16 AND 17*
TEST.66--*DATI TEST OF EA BITS 16 AND 17*
TEST.67 --*DATI NPR NON-EXISTANT MEMORY TEST*
TEST.70--*DATO NPR NON-EXISTANT MEMORY TEST*
TEST.71--*FLOATING 1 MAIN MEMORY TEST*
TEST.72--*FLOATING ZERO MAIN MEMORY TEST*
TEST.73--*MAIN MEMORY DUAL ADDRESSING TEST*
TEST.74--*MAR TEST*
TEST.75--*ALU C BIT TEST*
TEST.76--*(B) ALU TEST*
TEST.77--*(A) ALU TEST*
TEST.100--*(A+NOT B) ALU TEST*
TEST.101--*(AB) ALU TEST*
TEST.102--*(A+B) ALU TEST*
TEST.103--*(A XOR B) ALU TEST*
TEST.104--*(A PLUS B) ALU TEST*
TEST.105--*(2A W/C) ALU TEST*
TEST.106--*(A-B) ALU TEST*
TEST.107--*(ADD W/C) ALU TEST*
TEST.110--*(SUB W/C) ALU TEST*
TEST.111--*(INC A) ALU TEST*
TEST.112--*(2A) ALU TEST*
TEST.113--*(A PLUSC) ALU TEST*
TEST.114--*(2'S COMP SUB) ALU TEST*
TEST.115--*(DEC A) ALU TEST*
TEST.116--*(B) ALU TEST*
TEST.117--*(A) ALU TEST*
TEST.120--*(A + NOT B) ALU TEST*
TEST.121--*(AB) ALU TEST*
TEST.122--*(A+B) ALU TEST*
TEST.123--*(A XOR B) ALU TEST*
TEST.124--*(A PLUS B) ALU TEST*
TEST.125--*(2A W/C) ALU TEST*
TEST.126--*(A-B) ALU TEST*
TEST.127--*(ADD W/C) ALU TEST*
TEST.130--*(SUB W/C) ALU TEST*
TEST.131--*(INC A) ALU TEST*
TEST.132--*(2A) ALU TEST*
TEST.133--*(A W/C) ALU TEST*
TEST.134--*(2'S COMP W/C) ALU TEST*
TEST.135--*(DEC A) ALU TEST*
TEST.136.--*TEST OF PGM CLOCK BIT*
TEST.137--*MICRO PROCESSOR NOISE TEST*
TEST.140--*TEST OF BR RIGHT SHIFT*
TEST.141--*CRAM TEST OF JUMP(I) ALWAYS*
TEST.142--*CRAM TEST OF JUMP(I) ON C BIT SET*
TEST.143--*CRAM TEST OF JUMP(I) ON Z BIT SET*
TEST.144--*CRAM TEST OF JUMP(I) ON BR0 BIT SET*
TEST.145--*CRAM TEST OF JUMP(I) ON BR1 BIT SET*
TEST.146--*CRAM TEST OF JUMP(I) ON BR4 BIT SET*
TEST.147--*CRAM TEST OF JUMP(I) ON BR7 BIT SET*
TEST.150--*CRAM TEST OF JUMP(I) ON C BIT SET*
TEST.151--*CRAM TEST OF JUMP(I) ON Z BIT SET*
TEST.152--*CRAM TEST OF JUMP(I) ON BR0 BIT SET*
TEST.153--*CRAM TEST OF JUMP(I) ON BR1 BIT SET*
TEST.154--*CRAM TEST OF JUMP(I) ON BR4 BIT SET*
TEST.155--*CRAM TEST OF JUMP(I) ON BR7 BIT SET*



*A
STARTTING REGISTER ACCESS & W-R TESTING
STARTING MICRO PROCESSOR IBUS REG TESTS
STARTING NPR TESTING
STARTING MAIN MEMORY TESTING
STARTING ALU TESTING
STARTING JUMP(I) TESTING MICRO CODE WILL BE MODIFIED
END PASS 1.

KMC11 Status

The KMC11 is fully debugged and stable.

The diagnostic status is summarized below:

                           DIAGNOSTIC                              Result
------------------------------------------------------------------ ------
DSKMAA0 DECSYSTEM 2020 KMC11 DIAGNOSTICS                           Pass
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