IO Bus Bridge - KS10FPGA/KS10FPGA Wiki
The IO Bus Bridge interfaces the peripherals on the IO bus to the KS10 backplane bus. The KS10 FPGA implements register-compatible IO Bridges but does not attempt to implement the DEC Unibus hardware or protocol inside the FPGA. The IO Bus Bridge provides paging (Virtual Address/Physical Address translation) for the peripherals and a Status Register. The KS10 FPGA does not implement the (mostly undocumented) Maintenance Loopback Mode.
The DEC KS10 system architecture supported up to three IO Bridges that interfaced the KS10 backplane to standard Unibus Devices. These Unibus Adapters are commonly referred to as UBA1, UBA3, and UBA4; although the KS10 Technical Manual only documents the possibility of UBA1 and UBA3.
Apparently there is a limitation in the KS10 backplane wiring that prevents the use of UBA2, but UBA4 works in "non-standard" systems. TOPS-10 looks for devices on all four but never finds UBA2 installed. TOPS-20 only looks for UBA1, UBA3, and UBA4.
Lastly, and most importantly, the DSUBA diagnostic will test UBA1, UBA3, and UBA4 per below.
The IO Bus Bridge is fully parameterized so all of these configurations are supported by the UBA Verilog module. UBA1, UBA3, and UBA4 are implemented in the FPGA.
Normally UBA1 supports the RH11 Massbus Disk Controller and UBA3 supports everything else in the system. For now, UBA4 has four Unibus Exercisers (UBE) devices attached which are used to test the UBA.
The KS10 FPGA IO Bus implementation provides a 36-bit control/address bus and a 36-bit data bus whereas Unibus provides a 16-bit address bus and an 18-bit data bus. The KS10 FPGA IO Bus also uses significantly fewer clock cycles to implement the IO bus protocol.
UBA Register Set
UBA Status Register (UBASR)
The IO Bridge Status Register (UBASR) is a 36-bit IO register located at IO Address o763100 and is compatible with the Unibus Status Register of the DEC KS10.
UBA Maintenance Register (UBAMR)
The IO Bridge Maintenance Register (UBAMR) is a 36-bit IO register located at IO Address o763101 and controls the maintenance loopback feature of the IO Bus Bridge. The UBAMR is compatible with the Unibus Maintenance Register of the DEC KS10. Only some of the Maintenance Loopback features of the IO Bridge is implemented as required to pass some of the DSUBA diagnostics.
IO Address Translation (Paging)
The KS10 supports a 20-bit physical address while the IO devices only support a limited 16-bit address. The IO Bus Bridge provides a Paging mechanism that allows IO devices to access the entire physical memory of the KS10. This address translation is illustrated below.
Please be aware that KS10 address and data is big-endian (Bit 0, on the left, is the Most Significant Bit (MSB)) while the IO Bus address and data (like Unibus) is little-endian (Bit 0, on the right, is the Least Significant Bit (LSB).
UBA Paging Memory (UBAPAG)
The Address Translation is managed by a Translation (Paging) Memory that is located on the IO Bus Bridge.
The IO Bus Page Translation Memory is a sequence of memory locations at IO Address o76300 – o763077 and is register-compatible with the Unibus Paging Memory of the DEC KS10.
The paging memory is a lookup table that is used to translate the IO Virtual Address to the KS10 Physical Address. For each of the 64 Virtual Pages there are a possible 2048 Physical Pages
The format of the IO Bridge Paging Memory when written is summarized below.
The format of the IO Bridge Paging Memory when read is summarized below.
The bit definitions of the Paging RAM are defined below. The "Read Reverse", "Enable 16-bit IO Transfers", and "Fast Transfer Mode" bits in the paging RAM control the type of KS10 Bus to IO Bus (Unibus) translation that occurs in the IO Bridge.
A IO Bridge Page Failure occurs when:
Paging only occurs on memory operations and never occurs on IO operations.
In Fast Transfer Mode (FTM), the device transfers 36-bit data and the two LSBs must be zero. The more modern term for this would be an "alignment error".
IO Data Translation
The KS10 supports 36-bit IO addressing to internal devices, 16/18-bit IO addressing to UBA devices, and 8-bit addressing to UBA devices.
The DEC UBA data translation between the KS10 Backplane Bus and IO Bus is governed by a few rules:
Note: I don't really know if Read Reverse mode works with Byte Transfers or works in Fast Transfer Mode.
Byte and Word translation is based on the two LSBs of the IO address and is illustrated below.
Having acknowledged the DEC UBA design, the KS10 FPGA is not implemented the same way. As noted previously, the KS10 FPGA IO Bus is 36-bit wide and does not require the IO Bus Bridge to perform any of these data translation operations. The interface and IO translation between the IO device and the KS10 backplane is performed by the device. For example, the RH11 always operates in Fast Transfer Mode.
DSUBA Transcript With No UBEs Attached
DSUBA Transcript With UBEs Attached
Although there seems to be address definitions and interrupt definitions 12 Unibus Excercisers (UBEs), the DSUBA diagnostic probes for them in order and only uses the first four that are found - even if more are provided.
The diagnostic status of the KS10 IO Bus Bridge is summarized below: