IO Bus Bridge - KS10FPGA/KS10FPGA GitHub Wiki
The KS10 FPGA IO Bus Bridge interfaces the peripherals on the IO bus to the KS10 backplane bus. In the DEC KS10, the IO Bus was Unibus. Here the KS10 FPGA diverts significantly from the DEC design and implements a completely different, but compatible IO Bus design. This includes register-compatibility and compatible Virtual Address to Physical Address translation for the IO Bus. For these reasons, I've chosen to call this a IO Bus Bridge instead of a Unibus Adapter - although many places use the term Unibus and UBA to maintain consistency with the DEC KS10 documentation. This is discussed below.
The DEC KS10 system architecture supported up to three IO Bridges that interfaced the KS10 backplane to standard Unibus Devices. These Unibus Adapters are commonly referred to as UBA1, UBA3, and UBA4; although the KS10 Technical Manual only documents the possibility of UBA1 and UBA3.
Apparently there is a limitation in the KS10 backplane wiring that prevents the use of UBA2, but UBA4 works in "non-standard" systems. TOPS-10 looks for devices on all four but never finds UBA2 installed. TOPS-20 only looks for UBA1, UBA3, and UBA4.
Lastly, and most importantly, the DSUBA diagnostic will test UBA1, UBA3, and UBA4 per below. The KS10 FPGA does implement the mostly undocumented Maintenance Loopback Modes as required to pass the DSUBA diagnostics.
DECSYSTEM 2020 UNIBUS ADAPTER EXERCISER [ DSUBA ] VERSION 0.4, SV=0.3, CPU#=2020, MCV=130, MCO=470, HO=0, KASW=003740 000000 TTY SWITCH CONTROL ? - 0,S OR Y - 0 SWITCHES = 000000 000000 MEMORY MAP = FROM TO SIZE/K 00000000 03777777 1024 WHICH UNIBUS ADAPTER? (1,3,4):
The IO Bus Bridge is fully parameterized so all of these configurations are supported by the UBA Verilog module. UBA1, UBA3, and UBA4 are implemented in the FPGA. Each UBA adapter can currently support up to 5 devices.
In KS10 systems, UBA1 supports the RH11 Massbus Disk Controller exclusively. This is done to meet the disk performance requirements. UBA3 supports the RH11 Massbus Tape Controller and everything else in the KS10 system. For now, UBA4 has four Unibus Exercisers (UBE) devices attached which are used to test the UBA.
The KS10 FPGA IO Bus implementation provides a synchronous 36-bit non-multiplexed control/address bus and a 36-bit data bus whereas Unibus provides an asynchronous 16-bit address bus and an 18-bit data bus. The KS10 FPGA IO Bus also uses significantly fewer clock cycles to implement the IO bus protocol.
The IO Bridge Status Register (UBASR) is a 36-bit IO register located at IO Address o763100 and is compatible with the Unibus Status Register of the DEC KS10.
UBA Status Register
IO Bridge Status Register (UBASR) Definitions - IO Address 763100 |
|||
Bit(s) |
Mnemonic |
R/W |
Description |
18 |
TMO |
R/W |
Adapter Timeout The TMO bit is set under the following conditions:
The TMO bit is negated by:
|
19 |
BMD |
R |
Bad Memory Data Not implemented. Always read as zero. Writes are ignored. |
20 |
BPE |
R |
Bus Parity Error Not implemented. Always read as zero. Writes are ignored. |
21 |
NXD |
R/W |
Non Existent Device The NXD bit is asserted when accessing an IO device attached to this IO Bridge that does not exist; i.e., no IO device acknowledges a request at the IO address that was provided. The NXD bit is negated by:
|
22 |
- |
- |
Reserved Always read as zero. Writes are ignored. |
23 |
- |
- |
Reserved Always read as zero. Writes are ignored. |
24 |
HI |
R |
HI Interrupt HI is asserted when there is an active IRQ on BR7 or BR6. Writes are ignored. |
25 |
LO |
R |
LO Interrupt LO is asserted when there is an active IRQ on BR5 or BR4. Writes are ignored. |
26 |
PWR |
R |
Power Fail The PWR bit is asserted when any of the IO devices asserts the ACLO signal; otherwise PWR is negated. None of the proper IO devices generate the ACLO signal, however the PWR bit is tested by the Unibus Exerciser (UBE) in DSUBA TEST45. The KS10 FPGA version of the IO Bus does not implement the Unibus DCLO signal since it is not used by anything and is not tested.
Writes are ignored. |
28 |
DXF |
R/W |
Disable Transfer Not implemented. DXF is asserted by writing a '1' to DXF. DXF is negated by:
|
29 |
INI |
R/W |
Initialize. AKA IO Bridge Clear Writing '1' to INI resets all devices on this IO Bridge. The KS10 has a one-shot that asserts this signal for 1 μS. This bit remains asserted only for that period. |
30:32 |
PIH |
R/W |
Priority Interrupt High PIH maps the priority of the high priority device interrupts, devINTR[7] and devINTR[6], to the CPU interrupt priority defined by the PIH register. PIH is set by writing to this register. PIH is cleared by:
Note: There are seven CPU interrupt priorities - Priority 1 through Priority 7. Setting PIH to 0 disables all high priority interrupts from this IO Bridge. |
33:35 |
PIL |
R/W |
Priority Interrupt Low PIL maps the priority of the low priority device interrupts, devINTR[5] and devINTR[4], to the CPU interrupt priority defined by the PIL register. PIL is set by writing to this register. PIL is cleared by:
Note: There are seven CPU interrupt priorities - Priority 1 through Priority 7. Setting PIL to 0 disables all low priority interrupts from this IO Bridge. |
The IO Bridge Maintenance Register (UBAMR) is a 36-bit IO register located at IO Address o763101 and controls the maintenance loopback feature of the IO Bus Bridge. The UBAMR is compatible with the Unibus Maintenance Register of the DEC KS10. Only some of the Maintenance Loopback features of the IO Bridge is implemented as required to pass the DSUBA diagnostics.
UBA Maintenance Register
|
IO Bridge Maintenance Register (UBAMR) Definitions - IO Address 763101 |
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Bit(s) |
Mnemonic |
R/W |
Description |
0:34 |
- |
- |
Reserved. Always read as zero. Writes are ignored. |
35 |
MAINT |
W |
Maintenance Mode MAINT is asserted by writing a '1' to MAINT. MAINT is negated by:
Always read as zero. |
The KS10 supports a 20-bit physical address while the IO devices only support a limited 16-bit address. The IO Bus Bridge provides a Paging mechanism that allows IO devices to access the entire physical memory of the KS10. This address translation is illustrated below.
IO Bus Address Translation (Paging)
Please be aware that KS10 address and data is big-endian (Bit 0, on the left, is the Most Significant Bit (MSB)) while the IO Bus address and data (like Unibus) is little-endian (Bit 0, on the right, is the Least Significant Bit (LSB)).
The Address Translation is managed by a Translation (Paging) Memory that is located on the IO Bus Bridge.
The IO Bus Page Translation Memory is a sequence of memory locations at IO Address o76300 – o763077 and is register-compatible with the Unibus Paging Memory of the DEC KS10.
The paging memory is a lookup table that is used to translate the IO Virtual Address to the KS10 Physical Address. For each of the 64 Virtual Pages there are a possible 2048 Physical Pages.
The format of the IO Bridge Paging Memory when written is summarized below.
IO Bridge Paging RAM (Write)
The format of the IO Bridge Paging Memory when read is summarized below.
IO Bridge Paging RAM (Read)
The bit definitions of the Paging RAM are defined below. The "Read Reverse", "Enable 16-bit IO Transfers", and "Fast Transfer Mode" bits in the paging RAM control the type of KS10 Bus to IO Bus (Unibus) translation that occurs in the IO Bridge.
UBA Paging RAM Definitions - IO Addresses 763000-763077 |
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Bit(s) |
Mnemonic |
R/W |
Description |
5/18 |
RRV |
R/W |
Read Reverse In normal mode (not "Read Reverse" mode), when a 16-bit or 18-bit NPR operation occurs, the access to the Even Word occurs first and writes the entire 36-bit word. The access to the Odd Word is a Read-Pause-Write (or Read/Modify/Write) access. In Read Reverse mode, when a 16-bit or 18-bit Word is being accessed, the access to the Odd Word occurs first and is a Read-Pause-Write (or Read/Modify/Write) access. The access to the Even Word is also a Read-Pause-Write (or Read/Modify/Write) access. |
6/19 |
E16 |
R/W |
Enable 16-bit Enable 16-bit NPR operations and disable 18-bit NPR operations. |
7/20 |
FTM |
R/W |
Fast Transfer Mode. In this mode, reads from even words on Unibus are stored in the UBA and not immediately transferred to memory. When the odd word is accessed, the even word and odd word is transferred in a single 36-bit KS10 operation. This is used by the RH11 to efficiently transfer data been memory and disk drives. This is implemented as required for the maintenance loopback diagnostics. This bit is ignored for IO Bus transactions which are always 36-bit. |
8/21 |
VLD |
R/W |
Page valid. This bit is set when the page data is loaded. |
16:26 |
PPM |
R/W |
Physical Page Number. |
A IO Bridge Page Failure occurs when:
- IO Address Bit 17 is asserted. This bit must be zero for a memory operation.
- The paging data for this page is requests Fast Transfer Mode (FTM) and IO Address Bit 0 is asserted.
- The paging data for this page is requests Fast Transfer Mode (FTM) and IO Address Bit 1 is asserted.
- The paging data for this page is not valid (see VLD bit).
Paging only occurs on memory operations and never occurs on IO operations.
In Fast Transfer Mode (FTM), the device transfers 36-bit data and the two LSBs must be zero. The more modern term for this would be an "alignment error".
The KS10 supports 36-bit IO addressing to internal devices, 16/18-bit IO addressing to UBA devices, and 8-bit addressing to UBA devices.
The DEC UBA data translation between the KS10 Backplane Bus and IO Bus is governed by a few rules:
- In normal mode (not "Read Reverse" mode), when a 16-bit or 18-bit NPR operation occurs, the access to the Even Word normally occurs first and is a normal access. The access to the Odd Word is a Read-Pause-Write (or Read/Modify/Write) access.
- In Read Reverse mode, when a 16-bit or 18-bit NPR operation occurs, the access to the Odd Word occurs first and is a Read-Pause-Write (Read/Modify/Write) access. The access to the Even Word is also a Read-Pause-Write (Read/Modify/Write) access.
- In normal mode (not "Read Reverse" mode), when a Byte is being accessed, the access to the Even Word Low Byte occurs first and is a normal access. The accesses to the Even Word High Byte, Odd Word Low Byte, Odd Word High Byte follow in order and are Read-Pause-Write(Read/Modify/Write) accesses.
- In Fast Transfer Mode, accesses to Even Words are stored by the IO Bridge. When the Odd Word is accessed, the 36-bit result of these two operations are combined into a single 36-bit access.
Note: I don't really know if Read Reverse mode works with Byte Transfers or works in Fast Transfer Mode.
Byte and Word translation is based on the two LSBs of the IO address and is illustrated below.
IO Bus Byte and Word Translation into a 36-bit Word
UBA Byte and Word Address Translation |
|||
BYTE |
UBA |
UBA |
UBA Transaction Description |
0 |
0 |
0 |
Even word |
0 |
1 |
0 |
Odd word |
1 |
0 |
0 |
Even word, low byte |
1 |
0 |
1 |
Even word, high byte |
1 |
1 |
0 |
Odd word, low byte |
1 |
1 |
1 |
Odd word, high byte |
Having acknowledged the DEC UBA design, the KS10 FPGA is not implemented the same way. As noted previously, the KS10 FPGA IO Bus is 36-bit wide and does not require the IO Bus Bridge to perform any of these data translation operations. The interface and IO translation between the IO device and the KS10 backplane is performed by the device. For example, the RH11 always operates in Fast Transfer Mode.
Supported Device NPR Operations |
||||
Device |
NPR |
NPR |
NPR |
Comments |
DUP11 |
N/A |
No |
No |
Does not support NPR operations. |
DZ11 |
N/A |
No |
No |
Does not support NPR operations. |
KMC11 |
RPW |
Yes |
Yes |
Supports both memory and IO NPR operations. |
LP20 |
RPW |
Yes |
No |
Supports NPR operations to load translation RAM and to transfer printer data from memory to the character buffer. |
RH11 |
FTM |
Yes |
Yes |
Always Fast Transfer Mode (FTM) |
UBE |
FTM |
Yes |
Yes |
Testing only. |
SMMON CMD - DSUBA DECSYSTEM 2020 UNIBUS ADAPTER EXERCISER [ DSUBA ] VERSION 0.4, SV=0.3, CPU#=2020, MCV=130, MCO=470, HO=0, KASW=003740 000000 TTY SWITCH CONTROL ? - 0,S OR Y - 0 SWITCHES = 000000 000000 MEMORY MAP = FROM TO SIZE/K 00000000 03777777 1024 WHICH UNIBUS ADAPTER? (1,3,4):1 ***** NO EXERCISERS ON UNIBUS ***** - TESTING UNIBUS ADAPTER 1 ***** WARNING: NO EXERCISERS ON BUS,-UBE MEDIATED TESTS ABORTED ***** END PASS 1.
Although there seems to be address definitions and interrupt definitions 12 Unibus Exercisers (UBEs), the DSUBA diagnostic probes for them in order and only uses the first four that are found - even if more are provided.
SMMON CMD - DSUBA DECSYSTEM 2020 UNIBUS ADAPTER EXERCISER [ DSUBA ] VERSION 0.4, SV=0.3, CPU#=2020, MCV=130, MCO=470, HO=0, KASW=003740 000000 TTY SWITCH CONTROL ? - 0,S OR Y - 0 SWITCHES = 000000 000000 MEMORY MAP = FROM TO SIZE/K 00000000 03777777 1024 WHICH UNIBUS ADAPTER? (1,3,4):4 UBE BASE ADDRESS VECTOR ______________________________ 01 4770000 0510 02 4770020 0520 03 4770040 0530 04 4770060 0540 END PASS 1.
The diagnostic status of the KS10 IO Bus Bridge is summarized below:
DIAGNOSTIC Result
---------------------------------------------------------------- ------
DSUBAC0 DECSYSTEM 2020 UNIBUS ADAPTER EXERCISER . . . . . . . . Pass