The Host Computer System

All software development and FPGA firmware development is performed on a host computer that is attached to the KS10 FPGA target device.

Currently most of the development is performed on a Cygwin (Windows) system, for now. Gradually, the build system is being expanded to build the KS10 project using Linux tools and/or using the Windows System for Linux (WSL) tools. This tool expansion is on-going.

Numerous unix utilities are employed to automate the build processes. Performing these tasks manually would be onerous and prone to mistakes. There are no plan to expand the development tooling to use non-unix -like tools.

The Host Computer system is used to build the software, to build the FPGA firmware, and to build and run the simulation tooling.

Cloning the KS10 FPGA Github Repository

The KS10 FPGA software uses some submodules that are maintained outside of the KS10 FPGA repository. You must clone the repository as follows:

  
  $ cd <install_directory>
  $ git clone --recurse-submodules https://github.com/KS10FPGA/KS10FPGA

The Installation Tree

For your reference I've illustrated the directory structure of my build tree below.

Note: Some directories are private (for now) have been not been exported to github.

$ tree -d
.
├── Tape and Disk Images
│   ├── Console SDHC
│   ├── DE10-Nano Image
│   ├── KLAD Sources
│   ├── KS10 Diagnostics
│   ├── KS10 Formatter
│   ├── KS10 Microcode
│   ├── RED PACK 405A2
│   ├── TOPS10
│   └── TOPS20
├── code
│   ├── fpga_loader_prog
│   └── gpio
├── fpga
│   ├── de10_top
│   │   ├── ise
│   │   ├── iverilog
│   │   ├── quartus
│   │   └── questa
│   ├── ks10
│   │   ├── arb
│   │   ├── breakpoint
│   │   ├── cpu
│   │   │   └── useq
│   │   ├── csl
│   │   ├── debug
│   │   ├── dup11
│   │   ├── dz11
│   │   ├── kmc11
│   │   ├── lp20
│   │   ├── lp26
│   │   ├── mem
│   │   ├── mt
│   │   ├── rh11
│   │   ├── rpxx
│   │   │   └── sd
│   │   ├── trace
│   │   ├── uba
│   │   ├── ube
│   │   └── utils
│   │       ├── uart
│   │       └── usrt
│   └── testbench
├── maindec
├── microcode
│   ├── ITS
│   ├── V130
│   └── V130R1
├── tools
│   ├── asm10
│   ├── mtdump
│   ├── seqparse
│   └── tapeutils
└── wiki
    └── images
        ├── cpu
        ├── csl
        ├── dup11
        ├── dz11
        ├── hw
        ├── kmc11
        ├── lp20
        ├── lp26
        ├── mem
        ├── mt
        ├── rh11
        ├── rpxx
        └── uba

Building the Console Processor Executable

The KS10 Console Processor application is a multi-threaded Linux application that controls and interacts with the the KS10 processor.

The console software can be built four different ways:

cross-compiled on a Cygwin host, or
cross-compiled on a Linux host, or
cross-compiled on a Windows Subsystem for Linux (WSL) host, or
compiled natively on the target.

Of all the options, cross-compiling the software is definitely the fastest.

These build processes are illustrated below.

Yes I know that I run the DE10-Nano target as root. Yes I'm aware that there are good reasons not to do that.

Cygwin Software Build

The Cygwin build uses an ARM cross-compiler to buld the target software and then transfers the binary executable to the DE10-Nano target using Secure Copy (scp).

The installation procedure for the ARM cross-compiler is detailed in the Host Software section of this wiki.

Note: The executable is statically linked so that the libraries on the DE10-Nano don't have to match the libraries on the host system.

The software is built in the code directory as follows:

$ cd code
$ make
arm-none-linux-gnueabihf-g++ -static -Os -W -Wall -pthread -pipe -Wformat=0 commands.cpp config.cpp cursor.cpp dasm.cpp dz11.cpp dup11.cpp hist.cpp cmdline.cpp ks10.cpp lp20.cpp mt.cpp rp.cpp rh11.cpp tape.cpp main.cpp -o console
make xfer
make[1]: Entering directory '/cygdrive/f/pdpx/pdp10/ks10/code'
scp -B console root@ks10:/home/root/
console                                                                                                                 100% 4134KB   2.3MB/s   00:01
make[1]: Leaving directory '/cygdrive/f/pdpx/pdp10/ks10/code'

Windows Subsystem for Linux (WSL) Software Build

The WSL build uses an ARM cross-compiler to buld the target software and then transfers the binary executable to the DE10-Nano target using Secure Copy (scp).

The installation procedure for the ARM cross-compiler is detailed in the Host Software section of this wiki.

Note: The executable is statically linked so that the libraries on the DE10-Nano don't have to match the libraries on the host system.

The software is built in the code directory as follows:

$ cd code
$ make
arm-linux-gnueabihf-g++ -static -Os -W -Wall -pthread -pipe -Wformat=0 commands.cpp config.cpp cursor.cpp dasm.cpp dz11.cpp dup11.cpp hist.cpp cmdline.cpp ks10.cpp lp20.cpp mt.cpp rp.cpp rh11.cpp tape.cpp main.cpp -o console
make xfer
make[1]: Entering directory '/mnt/f/pdpx/pdp10/ks10/code'
scp -B console root@ks10:/home/root/
console                                                                                                                         100% 1102KB   5.0MB/s   00:00
make[1]: Leaving directory '/mnt/f/pdpx/pdp10/ks10/code'

On Target Software Build

The source files may be copied to the DE10-Nano target and compiled natively as follows:

$ make
g++  -O2 -W -Wall -pthread -pipe -Wformat=0 commands.cpp config.cpp cursor.cpp dasm.cpp dz11.cpp dup11.cpp hist.cpp cmdline.cpp ks10.cpp lp20.cpp mt.cpp rp.cpp rh11.cpp tape.cpp main.cpp -o console
make xfer
make[1]: Entering directory '/home/root'
make[1]: Nothing to be done for 'xfer'.
make[1]: Leaving directory '/home/root'

FPGA Firmware Tooling

For now, the FPGA build process requires the Cygwin environment using Quartus 18.1.

Quartus 18.1 for Windows FPGA Firmware Build Process

As stated above, the FPGA build process requires the Cygwin environment using Quartus 18.1.

Quartus 21.1 for Windows FPGA Firmware Build Process

I have Quartus 21.1 for Windows installed but the qsys-generate build fails using my scripts as well as when using the Quartus IDE. Apparently it is a known issue and the workaround is to use Linux. I tried the workaround described at: https://forum.rocketboards.org/t/de10-nano-manual-instructions-fail-to-compile-ghrd-on-ubuntu-solved/1282 and didn't have any success - but I haven't spent much time debugging this. All of the other Quartus 21.1 executables work properly.

Quartus 21.1 for Linux/WSL FPGA Firmware Build Process

I also have Quartus 21.1 for Linux using WSL installed. The qsys-generate build also fails using my script as well as when using the Quartus IDE. It fails differently -- it hangs forever with no progress after a certain point.

Both Quartus 21.1 for Windows and Quartus 21.1 for Linux both build the the rest of the FPGA firmware which is everything but the SOC. It is only qsys-generate that is broken.

I was also unable to make the Quartus Linux tool recognize the USB Programmer. It fails with a Error (213013): Programming hardware cable not detected message.

I tried all the fixes at: https://www.jackenhack.com/quartus-prime-fpga-usb-blaster-problems-ubuntu-18-04/. Nothing affected this issue. I think the issue is related to WSL not forwarding the USB device into the virtual machine and is not related to Linux. See below:

$ lsusb
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub

Building the FPGA Firmware

The FPGA Firmware build process is rather elaborate and roughly proceeds as follows:

Extract the microcode from the DEC microcode listing files. The KS10 FPGA contains two microcode ROMS: the Dispatch ROM and the Control ROM which are both part of the microsequencer. A pair of awk scripts (crom.awk and drom.awk) extract the microcode from the DEC microcode listing file and generate files that are used to initialize the two ROMS. Lastly, the KS10 CPU Serial Number is built into the microcode. The "crom.awk" microcode extraction tool also edits the microcode to store a non-default KS10 CPU Serial Number in the microcode.
Quartus "qsys-generate" (aka Plaform Designer) takes the system-on-a-chip (SOC) description files and generates the top level SOC verilog files which can built with the KS10 RTL files. The SOC description files include things like the interface beteen the FPGA fabric and the Intel Hard Processing System (HPS) This interface includes memory interfaces, peripheral interfaces, the AXI4-lite slave interface which is the primary interface between the KS10 and the ARM processors, interrupts, GPIO, etc.
"quartus-map" analyzes and synthesizes the design.
"quartus-fit" place-and-routes the design.
"quartus-asm" assembles the design and creates and SRAM Object File (".sof").
"quartus-sta" peforms a static timing analysis.
Optionally "quartus-pgm" programs the FPGA (not the flash) via the JTAG interface.

FPGA Firmware Build Rules

The fpga/makefile has several targets that are useful when building the FPGA firmware.

The default target simply builds the FPGA firmware and creates the "de10_ks10.sof" SRAM Object File. The "de10_ks10.sof" file is used later to program the FPGA. This is illustrated below:

$ make

The "pgm1" target will load whatever firmware is already built into the FPGA via the JTAG interface.

$ make pgm1

The "pgm" target builds the FPGA firmware, creates the "de10_ks10.sof" file, and loads the firmware into the FPGA via the JTAG interface as follows:

$ make pgm

A transcript of today's build of the FPGA is shown below. Obviously this just a 'snapshot' of the state of the design and will change as the design evolves.

Quartus is notorious for emitting a ton of "less than useful" (annoying) warnings and information messages during the build process. In general there is so junk in the output that it is difficult to find important messages that should not be ignored. I've done my best to filter out the noise and leave the genuinely interesting messages in the output transcript.

$ make pgm
Creating de10_top/quartus/de10_ks10.qsf
Creating de10_top/quartus/files.qsf
awk -v SERIALNUM=4097 -f ks10/cpu/useq/crom.awk < ks10/cpu/useq/ks10.mcr > ks10/cpu/useq/crom.dat
/cygdrive/c/intelFPGA_lite/18.1/quartus/bin64/quartus_map --read_settings_files=on --write_settings_files=off --rev=de10_ks10 --verilog_macro=QUARTUS \
--verilog_macro=SYNTHESIS --verilog_macro=SERIALNUM=4097 --verilog_macro=MAJOR_VER=\"00\" --verilog_macro=MINOR_VER=\"37\" --verilog_macro=CLKFRQ=12500000 \
--verilog_macro=SSRAMx18 --verilog_macro=RPXX_SIMSEEK --verilog_macro=RPXX_SIMDMD --verilog_macro=UBA1 --verilog_macro=RH11A --verilog_macro=UBA3 \
--verilog_macro=RH11B --verilog_macro=LP20 --verilog_macro=DZ11 --verilog_macro=DUP11 --verilog_macro=KMC11 --verilog_macro=UBA4 --verilog_macro=UBE1 \
--verilog_macro=UBE2 --verilog_macro=UBE3 --verilog_macro=UBE4  de10_top/quartus/de10_ks10
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions
    Info: and other software and tools, and its AMPP partner logic
    Info: functions, and any output files from any of the foregoing
    Info: (including device programming or simulation files), and any
    Info: associated documentation or information are expressly subject
    Info: to the terms and conditions of the Intel Program License
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Sat Mar 05 04:14:13 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off --rev=de10_ks10 --verilog_macro=QUARTUS --verilog_macro=SYNTHESIS \
--verilog_macro=SERIALNUM=4097 --verilog_macro=MAJOR_VER="00" --verilog_macro=MINOR_VER="37" --verilog_macro=CLKFRQ=12500000 --verilog_macro=SSRAMx18 \
--verilog_macro=RPXX_SIMSEEK --verilog_macro=RPXX_SIMDMD --verilog_macro=UBA1 --verilog_macro=RH11A --verilog_macro=UBA3 --verilog_macro=RH11B \
--verilog_macro=LP20 --verilog_macro=DZ11 --verilog_macro=DUP11 --verilog_macro=KMC11 --verilog_macro=UBA4 --verilog_macro=UBE1 --verilog_macro=UBE2 \
--verilog_macro=UBE3 --verilog_macro=UBE4 de10_top/quartus/de10_ks10
Info (20032): Parallel compilation is enabled and will use up to 16 processors
Info (12127): Elaborating entity "de10_ks10" for the top level hierarchy
Warning (10034): Output port "ESD_ADDR" at de10_ks10.v(160) has no driver File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 160
Warning (10034): Output port "ESD_SCLK" at de10_ks10.v(153) has no driver File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 153
Warning (10034): Output port "ESD_DO" at de10_ks10.v(155) has no driver File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 155
Warning (10034): Output port "ESD_CS_N" at de10_ks10.v(156) has no driver File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 156
Warning (10034): Output port "ESD_RST_N" at de10_ks10.v(157) has no driver File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 157
Warning (10034): Output port "ESD_RD_N" at de10_ks10.v(158) has no driver File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 158
Warning (10034): Output port "ESD_WR_N" at de10_ks10.v(159) has no driver File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 159
Warning (10030): Net "dupTXFIFO" at ks10.sv(347) has no driver or initial value, using a default initial value '0' File: F:/pdpx/pdp10/ks10/fpga/ks10/ks10.sv Line: 347
Warning (10030): Net "dupTXE" at ks10.sv(338) has no driver or initial value, using a default initial value '0' File: F:/pdpx/pdp10/ks10/fpga/ks10/ks10.sv Line: 338
Warning (10030): Net "dupRXF" at ks10.sv(348) has no driver or initial value, using a default initial value '0' File: F:/pdpx/pdp10/ks10/fpga/ks10/ks10.sv Line: 348
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus
Info (10041): Inferred latch for "dpreg[35]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[34]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[33]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[32]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[31]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[30]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[29]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[28]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[27]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[26]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[25]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[24]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[23]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[22]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[21]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[20]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[19]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[18]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[17]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[16]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[15]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[14]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[13]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[12]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[11]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[10]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[9]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[8]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[7]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[6]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[5]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[4]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[3]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[2]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[1]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10041): Inferred latch for "dpreg[0]" at cpu.sv(202) File: F:/pdpx/pdp10/ks10/fpga/ks10/cpu/cpu.sv Line: 202
Info (10264): Verilog HDL Case Statement information at debug.v(102): all case item expressions in this case statement are onehot File: F:/pdpx/pdp10/ks10/fpga/ks10/debug/debug.v Line: 102
Info (10264): Verilog HDL Case Statement information at uart_tx.v(392): all case item expressions in this case statement are onehot File: F:/pdpx/pdp10/ks10/fpga/ks10/utils/uart/uart_tx.v Line: 392
Info (19000): Inferred 15 megafunctions from design logic
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|RH11:uRH11B|RHDB:DB|mem_rtl_0"
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|KMC11:uKMC11|KMCMEM:uMEM|ram_rtl_0"
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|KMC11:uKMC11|KMCSEQ:uSEQ|kmcCRAM_MEM_rtl_0"
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|LP26:uLP26|lpDVFUDAT_rtl_0"
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|LP26:uLP26|lpLINBUF_rtl_0"
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|LP20:uLP20|LPRAMD:RAMD|ramDATA_rtl_0"
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|LP20:uLP20|LPRAMD:RAMD|ramCTRL_rtl_0"
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|DZ11:uDZ11|DZRBUF:RBUF|FIFO:RBUF|mem_rtl_0"
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|RH11:uRH11A|RHDB:DB|mem_rtl_0"
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|DEBUG:uDEBUG|FIFO:TRACE_BUFFER|mem_rtl_0"
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|CPU:uCPU|RAMFILE:uRAMFILE|ram_rtl_0"
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|CPU:uCPU|PAGER:uPAGER|pageTABLE_rtl_0"
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|CPU:uCPU|USEQ:uUSEQ|STACK:uSTACK|stack_rtl_0"
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|CPU:uCPU|USEQ:uUSEQ|CROM:uCROM|CROM_rtl_0"
    Info (276029): Inferred altsyncram megafunction from the following design logic: "soc_system:u0|KS10:ks10|CPU:uCPU|DROM:uDROM|DROM_rtl_0"
Warning (14284): Synthesized away the following node(s):
    Warning (14285): Synthesized away the following RAM node(s):
Warning (13039): The following bidirectional pins have no drivers
    Warning (13040): bidirectional pin "ESD_DIO" has no driver File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 161
Warning (13009): TRI or OPNDRN buffers permanently enabled
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "LED_PWR_N" is stuck at GND File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 148
    Warning (13410): Pin "LED_BOOT_N" is stuck at GND File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 150
    Warning (13410): Pin "ESD_SCLK" is stuck at GND File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 153
    Warning (13410): Pin "ESD_DO" is stuck at GND File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 155
    Warning (13410): Pin "ESD_CS_N" is stuck at GND File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 156
    Warning (13410): Pin "ESD_RST_N" is stuck at GND File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 157
    Warning (13410): Pin "ESD_RD_N" is stuck at GND File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 158
    Warning (13410): Pin "ESD_WR_N" is stuck at GND File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 159
    Warning (13410): Pin "ESD_ADDR[0]" is stuck at GND File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 160
    Warning (13410): Pin "ESD_ADDR[1]" is stuck at GND File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 160
    Warning (13410): Pin "ESD_ADDR[2]" is stuck at GND File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 160
    Warning (13410): Pin "ESD_ADDR[3]" is stuck at GND File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 160
    Warning (13410): Pin "ESD_ADDR[4]" is stuck at GND File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 160
Info (286031): Timing-Driven Synthesis is running on partition "Top"
Info (17049): 320 registers lost all their fanouts during netlist optimizations.
Info (286031): Timing-Driven Synthesis is running on partition "soc_system_hps_hps_io_border:border"
Info (144001): Generated suppressed messages file F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/output_files/de10_ks10.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 14 node(s), including 0 DDIO, 4 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 12 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "SW_BOOT_N" File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 146
    Warning (15610): No output dependent on input pin "SW_HALT_N" File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 147
    Warning (15610): No output dependent on input pin "ESD_DI" File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 154
    Warning (15610): No output dependent on input pin "KEY[0]" File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 163
    Warning (15610): No output dependent on input pin "KEY[1]" File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 163
    Warning (15610): No output dependent on input pin "SW[0]" File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 164
    Warning (15610): No output dependent on input pin "SW[1]" File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 164
    Warning (15610): No output dependent on input pin "SW[2]" File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 164
    Warning (15610): No output dependent on input pin "SW[3]" File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 164
    Warning (15610): No output dependent on input pin "SPARE0" File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 165
    Warning (15610): No output dependent on input pin "SPARE1" File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 166
    Warning (15610): No output dependent on input pin "SPARE2" File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 168
Info (21057): Implemented 27513 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 37 input pins
    Info (21059): Implemented 102 output pins
    Info (21060): Implemented 84 bidirectional pins
    Info (21061): Implemented 26305 logic cells
    Info (21064): Implemented 332 RAM segments
    Info (21065): Implemented 4 PLLs
    Info (21066): Implemented 1 delay-locked loops
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 42 warnings
    Info: Peak virtual memory: 5457 megabytes
    Info: Processing ended: Sat Mar 05 04:18:39 2022
    Info: Elapsed time: 00:04:26
    Info: Total CPU time (on all processors): 00:03:42
/cygdrive/c/intelFPGA_lite/18.1/quartus/bin64/quartus_fit --read_settings_files=off --write_settings_files=off --rev=de10_ks10 de10_top/quartus/de10_ks10
Info: *******************************************************************
Info: Running Quartus Prime Fitter
    Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions
    Info: and other software and tools, and its AMPP partner logic
    Info: functions, and any output files from any of the foregoing
    Info: (including device programming or simulation files), and any
    Info: associated documentation or information are expressly subject
    Info: to the terms and conditions of the Intel Program License
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Sat Mar 05 04:18:40 2022
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off --rev=de10_ks10 de10_top/quartus/de10_ks10
Info: qfit2_default_script.tcl version: #1
Info: Project  = de10_ks10
Info: Revision = de10_ks10
Info (20032): Parallel compilation is enabled and will use up to 16 processors
Info (119006): Selected device 5CSEBA6U23I7 for design "de10_ks10"
Info (21077): Low junction temperature is -40 degrees C
Info (21077): High junction temperature is 100 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Critical Warning (169085): No exact pin location assignment(s) for 72 pins of 223 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Critical Warning (174073): No exact pin location assignment(s) for 1 RUP, RDN, or RZQ pins of 1 total RUP, RDN or RZQ pins
    Info (174074): RUP, RDN, or RZQ pin HPS_DDR3_RZQ not assigned to an exact location on the device File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 78
Info (184020): Starting Fitter periphery placement operations
Warning (177007): PLL(s) placed in location FRACTIONALPLL_X0_Y15_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks
    Info (177008): PLL soc_system:u0|KS10:ks10|altera_pll:PLL|general[0].gpll~FRACTIONAL_PLL
Info (11178): Promoted 5 clocks (5 global)
    Info (11162): soc_system:u0|soc_system_hps:hps|soc_system_hps_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 with 4 fanout uses global clock CLKCTRL_G11
    Info (11162): soc_system:u0|KS10:ks10|altera_pll:PLL|outclk_wire[0]~CLKENA0 with 11740 fanout uses global clock CLKCTRL_G7
    Info (11162): soc_system:u0|KS10:ks10|altera_pll:PLL|outclk_wire[1]~CLKENA0 with 41 fanout uses global clock CLKCTRL_G5
    Info (11162): soc_system:u0|KS10:ks10|altera_pll:PLL|outclk_wire[3]~CLKENA0 with 41 fanout uses global clock CLKCTRL_G2
    Info (11162): soc_system:u0|KS10:ks10|altera_pll:PLL|outclk_wire[2]~CLKENA0 with 5 fanout uses global clock CLKCTRL_G6
Info (11191): Automatically promoted 1 clock (1 global)
    Info (11162): FPGA_CLK1_50~inputCLKENA0 with 60 fanout uses global clock CLKCTRL_G4
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:03
Warning (335093): The Timing Analyzer is analyzing 36 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
Info (332104): Reading SDC File: 'de10_ks10.sdc'
Warning (332174): Ignored filter at de10_ks10.sdc(45): SSRAM_CLK could not be matched with a clock File: F:/PDPx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.sdc Line: 45
Warning (332049): Ignored set_input_delay at de10_ks10.sdc(45): Argument -clock is an empty collection File: F:/PDPx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.sdc Line: 45
    Info (332050): set_input_delay  -clock [get_clocks SSRAM_CLK] -max  6.5 [get_ports {SSRAM_D*}] File: F:/PDPx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.sdc Line: 45
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {u0|ks10|PLL|general[0].gpll~FRACTIONAL_PLL|refclkin} -multiply_by 6 -duty_cycle 50.00 -name {u0|ks10|PLL|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} {u0|ks10|PLL|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}
    Info (332110): create_generated_clock -source {u0|ks10|PLL|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 24 -duty_cycle 50.00 -name {u0|ks10|PLL|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} {u0|ks10|PLL|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
    Info (332110): create_generated_clock -source {u0|ks10|PLL|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 24 -phase 90.00 -duty_cycle 50.00 -name {u0|ks10|PLL|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} {u0|ks10|PLL|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}
    Info (332110): create_generated_clock -source {u0|ks10|PLL|general[3].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 24 -phase 270.00 -duty_cycle 50.00 -name {u0|ks10|PLL|general[3].gpll~PLL_OUTPUT_COUNTER|divclk} {u0|ks10|PLL|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}
    Info (332110): create_generated_clock -source {u0|ks10|PLL|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 24 -phase 180.00 -duty_cycle 50.00 -name {u0|ks10|PLL|general[2].gpll~PLL_OUTPUT_COUNTER|divclk} {u0|ks10|PLL|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332104): Reading SDC File: 'soc_system/synthesis/submodules/altera_reset_controller.sdc'
Info (332104): Reading SDC File: 'soc_system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc'
Info (332104): Reading SDC File: 'soc_system/synthesis/submodules/hps_sdram_p0.sdc'
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332104): Reading SDC File: 'soc_system/synthesis/submodules/soc_system_hps_hps_io_border.sdc'
Info (332097): The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network.
    Info (332098): From: u0|hps|fpga_interfaces|hps2fpga_light_weight|clk  to: soc_system:u0|soc_system_hps:hps|soc_system_hps_fpga_interfaces:fpga_interfaces|hps2fpga_light_weight~FF_3425
    Info (332098): From: u0|hps|hps_io|border|i2c0_inst|i2c_clk  to: soc_system:u0|soc_system_hps:hps|soc_system_hps_hps_io:hps_io|soc_system_hps_hps_io_border:border|i2c0_inst~FF_3393
    Info (332098): From: u0|hps|hps_io|border|i2c1_inst|i2c_clk  to: soc_system:u0|soc_system_hps:hps|soc_system_hps_hps_io:hps_io|soc_system_hps_hps_io_border:border|i2c1_inst~FF_3393
    Info (332098): From: u0|hps|hps_io|border|usb1_inst|usb_ulpi_clk  to: soc_system:u0|soc_system_hps:hps|soc_system_hps_hps_io:hps_io|soc_system_hps_hps_io_border:border|usb1_inst~FF_3474
    Info (332098): Cell: u0|ks10|PLL|general[0].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk
    Info (332098): Cell: u0|ks10|PLL|general[0].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk
    Info (332098): Cell: u0|ks10|PLL|general[0].gpll~PLL_REFCLK_SELECT  from: clkin[0]  to: clkout
    Info (332098): Cell: u0|ks10|PLL|general[1].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk
    Info (332098): Cell: u0|ks10|PLL|general[2].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk
    Info (332098): Cell: u0|ks10|PLL|general[3].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Info (332152): The following assignments are ignored by the derive_clock_uncertainty command
Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 27 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):   20.000 FPGA_CLK1_50
    Info (332111):    2.500 HPS_DDR3_CK_N
    Info (332111):    2.500 HPS_DDR3_CK_P
    Info (332111):    2.500 HPS_DDR3_DQS_N[0]_OUT
    Info (332111):    2.500 HPS_DDR3_DQS_N[1]_OUT
    Info (332111):    2.500 HPS_DDR3_DQS_N[2]_OUT
    Info (332111):    2.500 HPS_DDR3_DQS_N[3]_OUT
    Info (332111):    2.500 HPS_DDR3_DQS_P[0]_IN
    Info (332111):    2.500 HPS_DDR3_DQS_P[0]_OUT
    Info (332111):    2.500 HPS_DDR3_DQS_P[1]_IN
    Info (332111):    2.500 HPS_DDR3_DQS_P[1]_OUT
    Info (332111):    2.500 HPS_DDR3_DQS_P[2]_IN
    Info (332111):    2.500 HPS_DDR3_DQS_P[2]_OUT
    Info (332111):    2.500 HPS_DDR3_DQS_P[3]_IN
    Info (332111):    2.500 HPS_DDR3_DQS_P[3]_OUT
    Info (332111): 1000.000 HPS_I2C0_SCL
    Info (332111): 1000.000 HPS_I2C1_SCL
    Info (332111):   16.666  HPS_USB_CLK
    Info (332111):   50.000      SD_SCLK
    Info (332111):    2.500 soc_system:u0|soc_system_hps:hps|soc_system_hps_hps_io:hps_io|soc_system_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk_write_clk
    Info (332111):    2.500 soc_system:u0|soc_system_hps:hps|soc_system_hps_hps_io:hps_io|soc_system_hps_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk
    Info (332111):    2.500 u0|hps|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock
    Info (332111):    3.333 u0|ks10|PLL|general[0].gpll~FRACTIONAL_PLL|vcoph[0]
    Info (332111):   80.000 u0|ks10|PLL|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
    Info (332111):   80.000 u0|ks10|PLL|general[1].gpll~PLL_OUTPUT_COUNTER|divclk
    Info (332111):   80.000 u0|ks10|PLL|general[2].gpll~PLL_OUTPUT_COUNTER|divclk
    Info (332111):   80.000 u0|ks10|PLL|general[3].gpll~PLL_OUTPUT_COUNTER|divclk
Info (176233): Starting register packing
Info (176235): Finished register packing
    Extra Info (176218): Packed 2 registers into blocks of type I/O output buffer
    Extra Info (176220): Created 1 register duplicates
Warning (15705): Ignored locations or region assignments to the following nodes
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:33
Info (170189): Fitter placement preparation operations beginning
Info (14951): The Fitter is using Advanced Physical Optimization.
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:33
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:31
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 12% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 42% of the available device resources in the region that extends from location X33_Y23 to location X44_Y34
Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info (170201): Optimizations that may affect the design's routability were skipped
    Info (170200): Optimizations that may affect the design's timing were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:50
Info (11888): Total time spent on timing analysis during the Fitter is 68.39 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:46
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Warning (169064): Following 2 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
    Info (169065): Pin ESD_DIO has a permanently disabled output enable File: F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/de10_ks10.v Line: 161
Info (169186): Following groups of pins have the same dynamic on-chip termination control
Info (144001): Generated suppressed messages file F:/pdpx/pdp10/ks10/fpga/de10_top/quartus/output_files/de10_ks10.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 9 warnings
    Info: Peak virtual memory: 9293 megabytes
    Info: Processing ended: Sat Mar 05 04:23:28 2022
    Info: Elapsed time: 00:04:48
    Info: Total CPU time (on all processors): 00:23:08
/cygdrive/c/intelFPGA_lite/18.1/quartus/bin64/quartus_asm --read_settings_files=off --write_settings_files=off --rev=de10_ks10 de10_top/quartus/de10_ks10
Info: *******************************************************************
Info: Running Quartus Prime Assembler
    Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions
    Info: and other software and tools, and its AMPP partner logic
    Info: functions, and any output files from any of the foregoing
    Info: (including device programming or simulation files), and any
    Info: associated documentation or information are expressly subject
    Info: to the terms and conditions of the Intel Program License
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Sat Mar 05 04:23:31 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off --rev=de10_ks10 de10_top/quartus/de10_ks10
Info (115030): Assembler is generating device programming files
Info (11878): Hard Processor Subsystem configuration has not changed and a Preloader software update is not required
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 5076 megabytes
    Info: Processing ended: Sat Mar 05 04:23:48 2022
    Info: Elapsed time: 00:00:17
    Info: Total CPU time (on all processors): 00:00:17
/cygdrive/c/intelFPGA_lite/18.1/quartus/bin64/quartus_pgm --mode=jtag --operation=p\;de10_top/quartus/output_files/de10_ks10.sof"@2" --quiet
Info: *******************************************************************
Info: Running Quartus Prime Programmer
    Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions
    Info: and other software and tools, and its AMPP partner logic
    Info: functions, and any output files from any of the foregoing
    Info: (including device programming or simulation files), and any
    Info: associated documentation or information are expressly subject
    Info: to the terms and conditions of the Intel Program License
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Sat Mar 05 04:23:48 2022
Info: Command: quartus_pgm --mode=jtag --operation=p;de10_top/quartus/output_files/de10_ks10.sof@2 --quiet
Info (213045): Using programming cable "DE-SoC [USB-1]"
Info (213011): Using programming file de10_top/quartus/output_files/de10_ks10.sof with checksum 0x03CDB876 for device 5CSEBA6U23@2
Info (209060): Started Programmer operation at Sat Mar 05 04:23:50 2022
Info (209016): Configuring device index 2
Info (209017): Device 2 contains JTAG ID code 0x02D020DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Sat Mar 05 04:23:53 2022
Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 4442 megabytes
    Info: Processing ended: Sat Mar 05 04:23:53 2022
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:01
/cygdrive/c/intelFPGA_lite/18.1/quartus/bin64/jtagconfig
1) DE-SoC [USB-1]
  4BA00477   SOCVHPS
  02D020DD   5CSEBA6(.|ES)/5CSEMA6/..

For now, the FPGA firmware is volatile - it is not stored in the Target Flash Memory and must be programmed each time the DE10-Nano is reset. This keeps the development platform in a factory default configuration during development. I have a tool that is close to complete that will will allow the KS10 software to load its own firmware into the FPGA at startup. Right now, it will load the FPGA firmware after the Quartus tool has loaded the FPGA firmware once. I suspect that there is a register that is uninitialized in my programming software.

Or we can program the Target Flash Memory when things are stable enough.

Building the Custom KS10 Development Tools

I generally try to use scripts (like awk) that don't require compiling in the build tooling. However, the are a few tools that require a host-based C/C++ complier to build. These tools, usage, and build process are listed below.

asm10

Asm10 is a tiny, very basic, nearly useless PDP10 assembler. I use it to create small standalone diagnostic programs. This program was authored by David Bridgham. It was slightly modified by me and is included here with his permission.

The asm10 documentation is located at:
https://github.com/KS10FPGA/KS10FPGA/tree/master/tools/asm10#readme

Build the asm10 tool as follows:

$ cd <install_directory>/tools/asm10
$ make
gcc -g -O3 -W -Wall -Wno-char-subscripts asm10.c ctype-asm.c opcodes.c pseudo.c sym.c -DKS10 -o asm10
$

asm10 is used to build the disk and tape bootloaders as well as test software.

tapeutils

The tapeutils are a group of programs that can read and write various types of PDP10 tape files. These originally were originally unix programs and is maintained externally to the KS10 project at: https://github.com/brouhaha/tapeutils and is configured as a submodule of the KS10 FPGA git module. Think of this as a git repository inside of a git repository.

For example, the RTL simulation tooling uses the t10backup program to extract diagnostic programs from diagnostic tape images.

Build tapeutils tool as follows:

$ cd <install_directory>/tools/tapeutils
$ make
cc -g -Wall   -c -o tapecopy.o tapecopy.c
cc -g -Wall   -c -o tapeio.o tapeio.c
cc -g  tapecopy.o tapeio.o   -o tapecopy
cc -g -Wall   -c -o tapedump.o tapedump.c
cc -g  tapedump.o tapeio.o   -o tapedump
cc -g -Wall   -c -o taperead.o taperead.c
cc -g  taperead.o tapeio.o   -o taperead
cc -g -Wall   -c -o tapewrite.o tapewrite.c
cc -g  tapewrite.o tapeio.o   -o tapewrite
cc -g -Wall   -c -o t10backup.o t10backup.c
In file included from t10backup.c:28:
t10backup.c: In function ‘downcase’:
t10backup.c:361:17: warning: array subscript has type ‘char’ [-Wchar-subscripts]
  361 |     if (isupper(*s)) *s = tolower(*s);
      |                 ^~
t10backup.c: In function ‘buildfilenames’:
t10backup.c:376:30: warning: ‘%s’ directive writing up to 99 bytes into a region of size between 0 and 99 [-Wformat-overflow=]
  376 |   sprintf (filespec [6], "%s.%s", filename, fileext);
      |                              ^~             ~~~~~~~
t10backup.c:376:3: note: ‘sprintf’ output between 2 and 200 bytes into a destination of size 100
  376 |   sprintf (filespec [6], "%s.%s", filename, fileext);
      |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc -g  t10backup.o tapeio.o   -o t10backup
cc -g -Wall   -c -o read20.o read20.c
In file included from read20.c:22:
read20.c: In function ‘main’:
read20.c:868:22: warning: array subscript has type ‘char’ [-Wchar-subscripts]
  868 |      argc && isdigit(**argv);
      |                      ^~~~~~
cc -g  read20.o tapeio.o   -o read20
cc -g -Wall   -c -o tapex.o tapex.c
In file included from tapex.c:28:
tapex.c: In function ‘downcase’:
tapex.c:298:17: warning: array subscript has type ‘char’ [-Wchar-subscripts]
  298 |     if (isupper(*s)) *s = tolower(*s);
      |                 ^~
tapex.c: In function ‘buildfilenames’:
tapex.c:313:27: warning: ‘%s’ directive writing up to 999 bytes into a region of size 100 [-Wformat-overflow=]
  313 |   sprintf (filespec [6], "%s.%s", filename, fileext);
      |                           ^~      ~~~~~~~~
tapex.c:313:3: note: ‘sprintf’ output between 2 and 1100 bytes into a destination of size 100
  313 |   sprintf (filespec [6], "%s.%s", filename, fileext);
      |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc -g  tapex.o tapeio.o   -o tapex
$

The tapeutils compilation will generate some warnings with modern compilers. You can safely ignore the warnings.

t10backup is used to extract the diagnostic programs from the diagnostic tape.

sav2verilog

When used in a simulation environment, the "sav2verilog" utility reads a PDP10 Save File (.SAV file), and creates verilog code that can be used to initalize the simulated KS10 SSRAM memory to the contents of the .SAV file. This allows the simulation to immediately beging executing the program without having to simulate reading the executable from the disk drive or tape drive. This significantly speeds up the simulation.

Specifically, "sav2verilog" program creates verilog 36-bit memory initialization code that can be read by the $readmemh() function.

The sav2verilog documentation is located at: https://github.com/KS10FPGA/KS10FPGA/tree/master/tools/sav2verilog#readme

Build sav2verilog tool as follows:

$ cd <install_directory>/tools/sav2verilog
$ make
gcc -O2 -W -Wall -Dx36 sav2verilog.c -o sav2verilog
$

An example of the output of the sav2verilogutility is illustrated below.

//
// Do not edit this file.
// It was created by ../../tools/sav2verilog/sav2verilog DSQDA.SAV DSQDA.DAT
//

@50
0c6000400		// mem[000120] = 030600002000
000003180		// mem[000121] = 000000030600
@5b
0c5fc31ff		// mem[000133] = 030577030777
@5f
000000003		// mem[000137] = 000000000003
@120
560003000		// mem[000440] = 254000030000
560001000		// mem[000441] = 254000010000
560002000		// mem[000442] = 254000020000
560000401		// mem[000443] = 254000002001
@200
560000411		// mem[001000] = 254000002021
560000418		// mem[001001] = 254000002030
560000429		// mem[001002] = 254000002051
560000457		// mem[001003] = 254000002127
fffffffff		// mem[001004] = 777777777777
cf58b2d2e		// mem[001005] = 636542626456
000000003		// mem[001006] = 000000000003
fffffffff		// mem[001007] = 777777777777
562000208		// mem[001010] = 254200001010
562000209		// mem[001011] = 254200001011
56200020a		// mem[001012] = 254200001012
56200020b		// mem[001013] = 254200001013
56200020c		// mem[001014] = 254200001014
56200020d		// mem[001015] = 254200001015
56200020e		// mem[001016] = 254200001016
56200020f		// mem[001017] = 254200001017
562000210		// mem[001020] = 254200001020

When the $readmemh() function is invoked, it starts reading data records and address records.

In this case, a data record is simply a 36-bit (9 hex digit) hexadecimal value that is to be stored at the current address. When the data record is read the current address is incremented.

An address record begins with an '@' (at) character and is followed by a hexadecimal address.

Both data records and address records can contain comments.

In summary, the information in the output file has two parts:

The information before the // comment character is used by the $readmemh()verilog function and is provided in hexadecimal.
The information after the // comment character can be read and understood by some humans and is provided in octal. For example, most real PDP-10 programmers will recognize opcode 254 in the data above as a JRST instruction.

For more information about the $readmemh() function, consult a good verilog reference.

sav2verilog is used to convert the .SAV files that are extracted from the diagnostic tape into a format that can be merged and loaded into the SSRAM memory.

Merge18 and merge36

These are awk scripts that concatinate diagnostic files together.

There are two versions: they both read 18-bit and 36-bit files; but merge18 emits an 18-bit file and merge36 emits a 36-bit file.

Co-simulating the FPGA RTL and PDP-10 Software

Simulating with ModelSim

A 'free' version of ModelSim is available with the older Quartus tools from the Intel website. I've done most of my simulation using ModelSim.

ModelSim Limitations

The 'free' version of ModelSim is limited to 10,000 lines of code. When the design exceeds 10,000 lines of code, the simualtor slows down by a factor of 10 (my guess) and becomes useless. The complete KS10 FPGA with all peripherals included exceeded that line count a long time ago.

In order to simulate the design, some of the peripherals need to be elided from the design. The fpga/makefile makes adding and deleting peripherals simple. Note: there is absolutely no issue fitting the entire design with all the peripherals in the FPGA - the FPGA is less than 25 percent utilized.

Simulating with QuestaSim

A 'free' version of QuestaSim is available with the newer Quartus tools from the Intel website. I've made a few changes to the makefile to support QuestaSim, but I have not used it very much.

Simulation using Icarus Verilog

I don't use Icarus Verilog for simulation very much anymore. It is slower than ModelSim. I do occasionally verify that "iverilog" can 'parse and elaborate' the design and I will fix syntax errors that might sneek into the design.

The advantage of Icarus Verilog is that it is Open Source and free to use.

Co-simulating FPGA and PDP-10 Software

It is often necessary to simulate the KS10 FPGA executing PDP-10 diagnostic software while simultaneously observing the FPGA behavior. Fortunately it has been a long time since the KS10 executed an diagnostic program incorrectly - excluding the known pager issues. At this point of time, most of the debugging involves peripheral devices that fail diagnostic tests.

The simulation is started in one of two ways:

The simulator can be configured to boot the KS10 just like on the target by copying the boot loader into memory and executing it. The boot loader will access the simulated RP06 boot disk and load the diagnostic monitor from the RP06 disk drive. This is generally the slower option of the two since the boot process spends a lot of time waiting for the disk drives.
The simulator can load the diagnostic monitor and the diagnostic program directly into simulated memory before the simulation is started. The 'make' tooling automates much of this process - but not all. The 'make' rules control scripts that extract the executables from tape files, merge executables together, and format the executable in a manner that way that verilog can used to initialize the simulated memory. Having gone to all the effort, the simulation startup is much faster.

I will illustrate how I simulate the KS10 FPGA and execute the diagnostics using method (2) above.

First, build all the tools described above. They are required for the simulation environment to build properly. I use a cygwin development environment and that will be used here.

During simulation, the KS10 FPGA RTL code emits a lot of debugging output that is written to files in the FPGA directory. In general, each devices provides it's own debugging stream this is directed to an output file.

Lets assume that I want to debug the RH11/TM03/TU45 tape system using the DSTUB diagostic. These are the steps I would follow:

Open a cygwin terminal. Issue the following commands:

$ cd <project directory>/fpga
$ touch cty_out.txt
$ tail -f cty_out.txt

Note: you only need to touch the "cty_out.txt" file once to create the file.

The simulator outputs the KS10 Console (CTY) to the file "cty_out.txt". The tail command will follow the KS10 Console output, character-by-character, on the cygwin terminal.

Open a second cygwin terminal. Issue the following commands:

$ cd <project directory>/fpga
$ touch mtstatus.txt
$ tail -f mtstatus.txt
Note: you only need to touch the "mtstatus.txt" file once to create the file.

The simulator outputs various types of magtape status information to the file "mtstatus.txt". The tail command will follow the file output, character by character, on the cygwin terminal.

Open a third cygwin terminal. Issue the following commands:

$ cd <project directory>/fpga
$ make DIAG=DSTUB vsim

When the build script (click to view) has completed, the Modelsim application will open in a new window. The modelsim transcript window will constantly update with the Time and the Program Counter (PC). Other less useful information will scroll by quickly.

Beware: Some of the diagnostic programs take more than a week to simulate from start to finish on my fastest computer. I usually use the KS10 FPGA target to isolate problems and then patch the diagnostic to start at the failing test instead of at starting the beginning of the diagnostic tests.

A screen capture of the terminals are shown below:

A screen capture of Modelsim application is shown below:

Note: The supported diagnostic names (and descriptions) are:

  DSKAA - DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 1)
  DSKAB - DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 2)
  DSKAC - DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 3)
  DSKAD - DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 4)
  DSKAE - DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 5)
  DSKAF - DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 6)
  DSKAG - DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 7)
  DSKAH - DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 8)
  DSKAI - DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 9)
  DSKAJ - DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC (10)
  DSKAK - DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC (11)
  DSKAL - DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC (12)
  DSKAM - DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC (13)
  DSKBA - DECSYSTEM 2020 BASIC INSTRUCTION RELIABILITY DIAGNOSTIC
  DSKCA - DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (1)
  DSKCB - DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (2)
  DSKCC - DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (3)
  DSKCD - DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (4)
  DSKCE - DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (5)
  DSKCF - DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (6)
  DSKCG - DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (7)
  DSKDA - DECSYSTEM 2020 CPU AND MEMORY RELIABILITY DIAGNOSTIC
  DSKEA - DECSYSTEM 2020 PAGING HARDWARE DIAGNOSTIC
  DSKEB - KS10 - CACHE DIAGNOSTIC
  DSKEC - KS10 - KL-PAGING DIAGNOSTIC
  DSKFA - DECSYSTEM 2020 INSTRUCTION TIMING DIAGNOSTIC
  DSDUA - DSDUA DECSYSTEM 2020 DUP-11 DIAGNOSTICS
  DSDZA - DECSYSTEM 2020 DZ11 ASYNC
  DSKMA - DECSYSTEM 2020 KMC11 DIAGNOSTICS
  DSLPA - DECSYSTEM 2020 LINE PRINTER DIAGNOSTIC [DSLPA]
  DSLTA - DECSYSTEM 2020 TELETYPE TEST
  DSMMA - DECSYSTEM 2020 KS10 1024K MEMORY DIAGNOSTIC (DSMMA)
  DSMMB - DECSYSTEM 2020 BLT/FLOATING 1-0 MEMORY EXERCISER TEST (DSMMB)
  DSMMC - DECSYSTEM 2020 FAST AC DIAGNOSTIC (DSMMC)
  DSMMD - DECSYSTEM 2020 MEMORY DIAGNOSTIC (DSMMD)
  DSRMA - DECSYSTEM 2020 RM03-RH11 BASIC DRIVE DIAGNOSTIC
  DSRMB - DECSYSTEM 2020 RH11 - RM03/RP06 - RELIABILITY DIAGNOSTIC
  DSRPA - DECSYSTEM 2020 RP06-RH11 BASIC DRIVE DIAGNOSTIC [DSRPA]
  DSTUA - DECSYSTEM 2020 RH11-TM02/03-TU45/TU77 BASIC DEVICE DIAGNOSTIC (DSTUA)
  DSTUB - DECSYSTEM 2020 RH11-TM02/03-TU16/TU45/TU77 RELIABILITY DIAGNOSTIC(DSTUB)
  DSUBA - DECSYSTEM 2020 UNIBUS ADAPTER EXERCISER  [ DSUBA ]

Extracting the RED PACK from Magtape

The DE10-Nano Console Program expects to find the RED PACK tape in the same directory and the console executable.

"red405a2.tap" is a magtape image of the diagnostics. It doesn't quite work yet, but the console will whine if it doesn't find the file. Because of the pager issues, the magtape will boot past the MTBOOT> prompt and BUGHLT.

Unzip the "red405a2.tap" tape file and copy it to the DE10 Nano as follows:

  
$ cd <install_directory>/Tape\ and\ Disk\ Images/RED\ PACK\ 405A2/
$ gunzip -k red405a2.tap.gz
$ scp red405a2.tap root@ks10:

Your process to copy the "red405a2.tap" file from the repository to the DE10 Nano will probably be different than what is illustrated above. For example, the secure copy command above assumes that the DE10-Nano's host name is "ks10", a root user name, and a password.

Extracting the KS10 Diagnostics from Magtape

The DE10-Nano Console Program also expects to find various diagnostic programs in the "diag" subdirectory of the directory where the console executable is located.

On the DE10-Nano, you will need to create a 'diag' sub-directory of the directory where the console application is located. I used the ssh command below to accomplish this.

Next, the "extract.sh" bash script unzips the tape file and uses the 't10backup' tape utility (described above) to extract all of the diagnostic programs from the "ks_diag_gs.tap.gz" tape file. All of the diagnostic programs are put in the "files" sub-directory on the host computer. If you didn't build the tape utilities above, this will fail.

Lastly, I use the scp command below to copy all the diagnostics from the 'files' directory on the host to the 'diag' directory on the DE10-Nano target.

  
$ cd <install_directory>/Tape\ and\ Disk\ Images/KS10\ Diagnostics/
$ ssh root@ks10
  
Last login: Sat Apr 16 16:44:36 2022
root@ks10:~# mkdir diag
root@ks10:~# exit
logout
Connection to ks10 closed.
  
$ ./extract.sh
$ scp files/* root@ks10:diag
  
beware.txt       100%  837    48.8KB/s   00:00
convrt.sav       100%   20KB 920.3KB/s   00:00
czdmgd.bin       100%   17KB 822.6KB/s   00:00
czm9ba.bin       100% 5061   306.7KB/s   00:00
czqmcf.bin       100%   17KB 878.2KB/s   00:00
decx11.bin       100%   39KB 786.4KB/s   00:00
decx11.cnf       100%   64     7.5KB/s   00:00
decx11.map       100%  724    37.2KB/s   00:00
diag.dn22        100%  225    19.2KB/s   00:00
dmpbot.bin       100%  461    38.5KB/s   00:00
dscda.sav        100%   32KB   1.5MB/s   00:00
dsdua.sav        100%   46KB   1.5MB/s   00:00
dsdza.sav        100%   32KB 604.6KB/s   00:00
dskaa.sav        100%   12KB 647.4KB/s   00:00
dskab.sav        100%   13KB 944.3KB/s   00:00
dskac.sav        100% 9284   593.8KB/s   00:00
dskad.sav        100%   10KB 478.6KB/s   00:00
dskae.sav        100% 7779   385.2KB/s   00:00
dskaf.sav        100%   10KB 552.6KB/s   00:00
dskag.sav        100% 4559   280.3KB/s   00:00
dskah.sav        100%   20KB   1.0MB/s   00:00
dskai.sav        100%   23KB 418.3KB/s   00:00
dskaj.sav        100%   16KB 649.4KB/s   00:00
dskak.sav        100%   30KB   1.3MB/s   00:00
dskal.sav        100%   32KB   1.3MB/s   00:00
dskam.sav        100%   20KB 385.1KB/s   00:00
dskba.sav        100%   61KB   1.6MB/s   00:00
dskca.sav        100%   16KB 829.5KB/s   00:00
dskcb.sav        100% 8069   408.5KB/s   00:00
dskcc.sav        100%   16KB 321.8KB/s   00:00
dskcd.sav        100%   30KB   1.5MB/s   00:00
dskce.sav        100%   24KB   1.2MB/s   00:00
dskcf.sav        100%   45KB 805.8KB/s   00:00
dskcg.sav        100%   30KB   1.5MB/s   00:00
dskda.sav        100%   68KB   1.5MB/s   00:00
dskea.sav        100%   25KB 986.9KB/s   00:00
dskeb.sav        100%   18KB   2.2MB/s   00:00
dskec.sav        100%   15KB 758.1KB/s   00:00
dskfa.sav        100% 8729   396.2KB/s   00:00
dskma.sav        100%   48KB   2.2MB/s   00:00
dslpa.sav        100%   74KB   1.6MB/s   00:00
dslta.sav        100% 4649   265.1KB/s   00:00
dsmma.sav        100%   21KB 412.0KB/s   00:00
dsmmb.sav        100% 3389   206.0KB/s   00:00
dsmmc.sav        100% 9839   477.7KB/s   00:00
dsmmd.sav        100% 6939   463.6KB/s   00:00
dsrha.sav        100%   28KB   1.3MB/s   00:00
dsrma.sav        100%  119KB   2.9MB/s   00:00
dsrmb.sav        100%  119KB   2.5MB/s   00:00
dsrpa.sav        100%  125KB   1.8MB/s   00:00
dstua.sav        100%  113KB   3.6MB/s   00:00
dstub.sav        100%   60KB   2.1MB/s   00:00
dsuba.sav        100%   31KB 525.9KB/s   00:00
dsxla.inp        100% 4332   288.5KB/s   00:00
dump0.dmp        100%   70KB   1.7MB/s   00:00
dzdmeb.bin       100%   17KB   1.1MB/s   00:00
dzdmfb.bin       100%   19KB 341.8KB/s   00:00
dzdmhb.bin       100%   12KB 596.8KB/s   00:00
gkaaa0.bic       100% 9561   808.2KB/s   00:00
gkabc0.bic       100%   10KB 916.3KB/s   00:00
ks10.mcl         100%  276KB   3.3MB/s   00:00
ks10.mcr         100% 1111KB   5.9MB/s   00:00
ks10.ram         100%   30KB   1.6MB/s   00:00
ks10.rsq         100% 5120   275.9KB/s   00:00
ks10.uld         100%  103KB   3.3MB/s   00:00
red-tape-3.txt   100%    0     0.0KB/s   00:00
smapt.hlp        100%  567    36.7KB/s   00:00
smapt.sav        100% 7305   373.0KB/s   00:00
smbc2.exe        100%   85KB   2.2MB/s   00:00
smbc2.sav        100%   78KB   2.3MB/s   00:00
smcpu.cmd        100%  402    20.6KB/s   00:00
smddt.hlp        100% 4521   140.8KB/s   00:00
smddt.sav        100%   17KB 766.3KB/s   00:00
smfile.exe       100%  105KB   2.9MB/s   00:00
smfile.hlp       100%  811    50.1KB/s   00:00
smfile.txt       100% 9441   494.5KB/s   00:00
smflt.cmd        100%  397    23.7KB/s   00:00
smmag.exe        100%   22KB   1.1MB/s   00:00
smmag.sav        100%   11KB 690.7KB/s   00:00
smmon.exe        100%   22KB   1.0MB/s   00:00
smmon.sav        100%   16KB 293.8KB/s   00:00
smtape.dir       100% 6981   364.7KB/s   00:00
smtape.mta       100% 1120    66.2KB/s   00:00
smtape.ram       100%   30KB   1.3MB/s   00:00
smtape.rdi       100% 2556   153.3KB/s   00:00
smtape.sav       100%   18KB 821.3KB/s   00:00
smusr.cmd        100%  354    23.2KB/s   00:00
subsm.sav        100%   14KB   1.0MB/s   00:00
subusr.sav       100%   11KB 671.3KB/s   00:00
zdldb0.bin       100%   12KB 256.0KB/s   00:00
zdpbbx.bin       100%   16KB 916.6KB/s   00:00
zdpcbx.bin       100%   14KB 741.1KB/s   00:00
zdpdbx.bin       100%   14KB 759.0KB/s   00:00
zdpea0.bin       100% 7650   471.2KB/s   00:00
zdpfb0.bin       100% 2550   138.2KB/s   00:00

Summary: My DE10-Nano directory tree looks like:

$ tree -a

.
├── .ks10
│   ├── dup11.cfg
│   ├── dz11.cfg
│   ├── lp20.cfg
│   ├── mt.cfg
│   └── rp.cfg
├── cmdline.cpp
├── cmdline.hpp
├── commands.cpp
├── commands.hpp
├── config.cpp
├── config.hpp
├── console
├── cursor.cpp
├── cursor.hpp
├── dasm.cpp
├── dasm.hpp
├── diag
│   ├── beware.txt
│   ├── convrt.sav
│   ├── czdmgd.bin
│   ├── czm9ba.bin
│   ├── czqmcf.bin
│   ├── decx11.bin
│   ├── decx11.cnf
│   ├── decx11.map
│   ├── diag.dn22
│   ├── dmpbot.bin
│   ├── dscda.sav
│   ├── dsdua.sav
│   ├── dsdza.sav
│   ├── dskaa.sav
│   ├── dskab.sav
│   ├── dskac.sav
│   ├── dskad.sav
│   ├── dskae.sav
│   ├── dskaf.sav
│   ├── dskag.sav
│   ├── dskah.sav
│   ├── dskai.sav
│   ├── dskaj.sav
│   ├── dskak.sav
│   ├── dskal.sav
│   ├── dskam.sav
│   ├── dskba.sav
│   ├── dskca.sav
│   ├── dskcb.sav
│   ├── dskcc.sav
│   ├── dskcd.sav
│   ├── dskce.sav
│   ├── dskcf.sav
│   ├── dskcg.sav
│   ├── dskda.sav
│   ├── dskea.sav
│   ├── dskeb.sav
│   ├── dskec.sav
│   ├── dskfa.sav
│   ├── dskma.sav
│   ├── dslpa.sav
│   ├── dslta.sav
│   ├── dsmma.sav
│   ├── dsmmb.sav
│   ├── dsmmc.sav
│   ├── dsmmd.sav
│   ├── dsrha.sav
│   ├── dsrma.sav
│   ├── dsrmb.sav
│   ├── dsrpa.sav
│   ├── dstua.sav
│   ├── dstub.sav
│   ├── dsuba.sav
│   ├── dsxla.inp
│   ├── dump0.dmp
│   ├── dzdmcb.bin
│   ├── dzdmeb.bin
│   ├── dzdmfb.bin
│   ├── dzdmhb.bin
│   ├── gkaaa0.bic
│   ├── gkabc0.bic
│   ├── ks10.mcl
│   ├── ks10.mcr
│   ├── ks10.ram
│   ├── ks10.rsq
│   ├── ks10.uld
│   ├── red-tape-3.txt
│   ├── smapt.hlp
│   ├── smapt.sav
│   ├── smbc2.exe
│   ├── smbc2.sav
│   ├── smcpu.cmd
│   ├── smddt.hlp
│   ├── smddt.sav
│   ├── smfile.exe
│   ├── smfile.hlp
│   ├── smfile.txt
│   ├── smflt.cmd
│   ├── smmag.exe
│   ├── smmag.sav
│   ├── smmon.exe
│   ├── smmon.sav
│   ├── smtape.dir
│   ├── smtape.mta
│   ├── smtape.ram
│   ├── smtape.rdi
│   ├── smtape.sav
│   ├── smusr.cmd
│   ├── subsm.sav
│   ├── subusr.sav
│   ├── zdldb0.bin
│   ├── zdpbbx.bin
│   ├── zdpcbx.bin
│   ├── zdpdbx.bin
│   ├── zdpea0.bin
│   └── zdpfb0.bin
├── dup11.cpp
├── dup11.hpp
├── dz11.cpp
├── dz11.hpp
├── hist.cpp
├── hist.hpp
├── ks10.cpp
├── ks10.hpp
├── lp20.cpp
├── lp20.hpp
├── main.cpp
├── makefile
├── mt.cpp
├── mt.hpp
├── pty.cpp
├── red405a2.tap
├── rh11.cpp
├── rh11.hpp
├── rp.cpp
├── rp.hpp
├── tape.cpp
├── tape.hpp
├── uba.hpp
└── vt100.hpp

Initializing the RP06 Disk Drives

The KS10 FPGA currently supports an array of eight RP06 disk drives that uses a single SD Card as storage media for all eight disk drives. As such, the SD Card that is used by the RP06 Disk Array must be partitioned for the eight disk drives and each partition must be formatted with a PDP-10 filesystem.

In order to keep things simple, the Massbus Disk Controller uses the same 'bits-on-disk' format as SIMH. This allows SIMH to be used to create disk images. Unlike SIMH, the PDP-10 filesystem is NOT a file inside a FAT32/NTFS/HPFS or some other recognizable filesystem; the PDP-10 filesystem is just raw data that is binary transferred to the SD Card.

Your host computer will see the PDP-10 formatted SD Card as an unformatted SD Card and may even offer to format it for you. Don't do that.

Because there are many generations of somewhat compatible SD Cards, each with somewhat different characteristics, the Massbus Disk Controller firmware only supports 8 GB to 32 GB SDHC cards. In general, SDSC-type cards are too small to support the disk array and 64 GB (and larger) SDXC-type cards have a different electrical interface.

Although the system seems work with many difference different brands of SD Cards, I generally do all my testing with SanDisk brand cards.

Background

By default, the Massbus Disk Controller is configured to support eight RP06 Massbus disk drives. The RP06 Massbus Disk Drive is the largest disk that is generally supported by all available versions of DEC TOPS-10 and TOPS-20.

Although the Massbus Disk Controller could in theory be configured for other DEC disk drives, I've only tested it using the RP06 configuration.

The description of the Massbus Disk Controller is available from https://github.com/KS10FPGA/KS10FPGA/wiki/RPxx-Disk-Simulator.

Disk Partitioning

At this point it is necessary to explain the SDHC Card partitioning - which is very simple. The SD Card stores data in sectors that are addressed using a Linear Sector Address. Each RP06 disk drive is allocated a 1 GB address space and storage on the SDHC Card. The first RP06 disk, UNIT 0, occupies the first 1 GB of storage. The second RP06 disk, UNIT 1, occupies the second 1 GB of storage, etc. The fixed-sized 1 GB partitions makes the disk addressing simple and allows this partitioning scheme to work with the largest Massbus disk drives like the RP07.

In this case, efficiency is complicated and storage is cheap.

Disk Formatting

The github repository has 3 compressed (.gz) RP06 disk images that reside in the fpga/testbench directory. When unzipped, these images are used by the SD Card Simulator when simulating the KS10 FPGA and are also used as the source for the disk images on the target SD Card. These compressed disk images are: dskb.rp06.gz, dskc.rp06.gz, and red405a2.rp06.gz.

I think I got the TOPS-10 V7.4 DSKB image and the DSKC image from: http://www.steubentech.com/~talon/pdp10/

The TOPS-20 RED405A2 image is a RED Pack image that I created as using the procedure described in the WIKI section entitled "Creating the REDPACK".

Until the pager issues are resolved, I just use the REDPACK image.

The formatting procedure simply copies these disk images to the correct locations on the SD Card.

Cygwin Programming Procedure

To program the RP06 Disk Array, you will need an SD Card Reader/Writer for your host computer. I use a very inexpensive Sabrent CR-BMC3 Reader/Writer - but surely every Reader/Writer will work.

Please read the following section very carefully.

Selecting the correct device for the SD Card is a little tricky under Cygwin.

Step 1: Select the disk device

Open a cygwin shell with administrator privledges.

The escalated privledges should be a warning that 'really bad things will happen' if you are careless following this procedure.

First, we need to determine the device to which the PDP-10 data will be written.

If you select the wrong device, this procedure will corrupt the destination disk drive and perhaps make your host computer unusable. You will certainly lose all of the data on that device. Be very careful.

To lessen the probability of doing something stupid that I will regret, I've created some rules in the Makefile that formalizes and semi-automates this process.

Lastly, be aware that disk devices are not static. They move around especially if you plug the SD Card Reader into a different USB Port. Use this procedure every time you program the SD Card.

To start, navigate to the fpga/testbench directory as follows:

$ cd <directory>/fpga/testbench

Install the SD Card in a USB-based SD Card reader and type the make check command. My host computer responds as follows. Yours will be different.

$ make check
cat /proc/partitions
major minor  #blocks  name   win-mounts

    8     0 1953514584 sda
    8     1    460800 sda1
    8     2    204800 sda2
    8     3 1952248745 sda3   C:\
    8     4    599040 sda4
    8    16 1953514584 sdb
    8    17 1953511424 sdb1   F:\
    8    32  30870528 sdc
    8    33  30870480 sdc1   S:\
    8    48         0 sdd
    8    64         0 sde
    8    80  15558144 sdf
    8    81  15558144 sdf1   M:\
    8    96         0 sdg
    8   112         0 sdh
    8   128     10240 sdi
    8   129      9216 sdi1   E:\

Device is currently /dev/sde

Because an 16 GB SD Card was inserted into the reader, it is plausible that /dev/sdf is the device of interest by examining the size of the storage associated with the device.

The last line also indicates that the Makefile is configured to program the /dev/sdedisk device - which is probably the wrong device.

I don't know about you - but I'm not willing to destroy one of my computer's filesystems by accidently writing a PDP-10 filesystem over the top of it.

We need to change the makefile to use the correct device and we need to verify the assumption that /dev/sdf is the correct device to use.

Edit the makefile and change the line:

DEV   := sde

DEV   := sdf

Editing the makefile will configure the makefile such that the device to be programmed is now /dev/sdf.

Next, unplug the SD Card from the reader and re-issue the same command:

$ make check
cat /proc/partitions
major minor  #blocks  name   win-mounts

    8     0 1953514584 sda
    8     1    460800 sda1
    8     2    204800 sda2
    8     3 1952248745 sda3   C:\
    8     4    599040 sda4
    8    16 1953514584 sdb
    8    17 1953511424 sdb1   F:\
    8    32  30870528 sdc
    8    33  30870480 sdc1   S:\
    8    48         0 sdd
    8    64         0 sde
    8    80         0 sdf
    8    96         0 sdg
    8   112         0 sdh
    8   128     10240 sdi
    8   129      9216 sdi1   E:\

Device is currently /dev/sdf

Note that size of /dev/sdf is now zero. That makes me more confident that /dev/sdf is the correct device to write the PDP-10 filesystem image to.

Verify that the last line of the output of this command, Device is currently /dev/sdf in this example, is correct for your installation.

Remove and replace your SD Card as often as necessary to convince yourself beyond doubt that you've identified the proper disk device.

Step 2: Programming the selected disk device

If you are not completely certain that you've selected the correct disk device - Stop Now!

Reinstall the SD Card into the reader.

For now, the Makefile rule will only program UNIT0, UNIT1, and UNIT2. UNIT3 through UNIT7 are not programmed.

Type the following command. Read all the warnings. If you are OK with proceeding, type YES at the prompt.

This procedure takes about 35 minutes on my very fast host computer mostly because the SD Card is very slow.

$ make rp06_disk

The disk /dev/sdf is partitioned as follows:
    8    80  15558144 sdf
    8    81  15558144 sdf1   M:\

This script will destroy all of the data on /dev/sdf
This script will destroy all of the data on /dev/sdf
This script will destroy all of the data on /dev/sdf

You've been warned.  If you don't know what you're doing.   Stop now!

Are you sure you want to do that? [YES/NO] YES
This will take a while.  Please be patient.

Programming UNIT0:
314793472 bytes (315 MB, 300 MiB) copied, 767 s, 410 kB/s
615600+0 records in
615600+0 records out
315187200 bytes (315 MB, 301 MiB) copied, 767.872 s, 410 kB/s

Programming UNIT1:
314801152 bytes (315 MB, 300 MiB) copied, 774 s, 407 kB/s
615600+0 records in
615600+0 records out
315187200 bytes (315 MB, 301 MiB) copied, 774.876 s, 407 kB/s

Programming UNIT2:
218776576 bytes (219 MB, 209 MiB) copied, 541 s, 404 kB/s
427624+0 records in
427624+0 records out
218943488 bytes (219 MB, 209 MiB) copied, 541.389 s, 404 kB/s

Install this SD Card into the KS10 IO Board's SD Card slot.

WSL Programming Procedure

I haven't figure out how to access an unformatted SD Card. It doesn't show up as a device in the /dev directory.

Linux Programming Procedure

This will be very similar to Cygwin.

Host Computer - KS10FPGA/KS10FPGA GitHub Wiki

The Host Computer System

Cloning the KS10 FPGA Github Repository

The Installation Tree

Building the Console Processor Executable

Cygwin Software Build

Windows Subsystem for Linux (WSL) Software Build

On Target Software Build

FPGA Firmware Tooling

Quartus 18.1 for Windows FPGA Firmware Build Process

Quartus 21.1 for Windows FPGA Firmware Build Process

Quartus 21.1 for Linux/WSL FPGA Firmware Build Process

Building the FPGA Firmware

FPGA Firmware Build Rules

Building the Custom KS10 Development Tools

asm10

tapeutils

sav2verilog

Merge18 and merge36

Co-simulating the FPGA RTL and PDP-10 Software

Simulating with ModelSim

ModelSim Limitations

Simulating with QuestaSim

Simulation using Icarus Verilog

Co-simulating FPGA and PDP-10 Software

Extracting the RED PACK from Magtape

Extracting the KS10 Diagnostics from Magtape

Initializing the RP06 Disk Drives

Background

Disk Partitioning

Disk Formatting

Cygwin Programming Procedure

Step 1: Select the disk device

Step 2: Programming the selected disk device

WSL Programming Procedure

Linux Programming Procedure

⚠️ GitHub.com Fallback ⚠️

Host Computer - KS10FPGA/KS10FPGA GitHub Wiki

The Host Computer System

Cloning the KS10 FPGA Github Repository

The Installation Tree

Building the Console Processor Executable

Cygwin Software Build

Windows Subsystem for Linux (WSL) Software Build

On Target Software Build

FPGA Firmware Tooling

Quartus 18.1 for Windows FPGA Firmware Build Process

Quartus 21.1 for Windows FPGA Firmware Build Process

Quartus 21.1 for Linux/WSL FPGA Firmware Build Process

Building the FPGA Firmware

FPGA Firmware Build Rules

Building the Custom KS10 Development Tools

asm10

tapeutils

sav2verilog

Merge18 and merge36

Co-simulating the FPGA RTL and PDP-10 Software

Simulating with ModelSim

ModelSim Limitations

Simulating with QuestaSim

Simulation using Icarus Verilog

Co-simulating FPGA and PDP-10 Software

Extracting the RED PACK from Magtape

Extracting the KS10 Diagnostics from Magtape

Initializing the RP06 Disk Drives

Background

Disk Partitioning

Disk Formatting

Cygwin Programming Procedure

Step 1: Select the disk device

Step 2: Programming the selected disk device

WSL Programming Procedure

Linux Programming Procedure

⚠️ **GitHub.com Fallback** ⚠️

⚠️ GitHub.com Fallback ⚠️