The DZ11 is an asynchronous multiplexer that provides an interface between the KS10 processor and eight asynchronous serial ports. It provides a means to control baud rate, character length, number of stop bits, parity, and transmitter/receiver interrupts for each of the eight serial ports. Lastly, the DZ11 provides some FIFO buffering (DEC called it a SILO) so that the KS10 processor did not need to service the DZ11 on every character that was received.
A block diagram of the DZ11 interface is illustrated below.
The DZ11 module is fully parameterized for IO Base Address, Interrupt Number, Interrupt Vector, and supports the four device configuration. The DZ11 configuration which is documented in the Appendix B.3 of the KS10 Technical Manual is summarized below.
The KS10 FPGA currently is only configured for the DZ11 at the 3760010 IO Base Address.
Although the DZ11 supports 8 serial interface, the KS10 FPGA evaluation board only provides two TTY interfaces. The other six TTY interfaces are tied-off internally.
I have been thinking more and more about providing an alternate DZ11 design that routes the 8 TTY ports through an Ethernet interface. The DZ11 has a FIFO for the receive data which would make a clean interface between a telnet-like daemon in the console and the remainder of the DZ11 hardware. Something similar could be implemented for the transmit data.
The DZ11 Technical Manual is available from http://bitsavers.org/pdf/dec/unibus/EK-DZ110-TM-002_DZ11_Asynchronous_Multiplexer_Technical_Manual_Oct78.pdf
The KS10 FPGA implementation of the DZ11 attempts to be register compatible with the DEC DZ11. The register interface is summarized in the following sections.
A summary of DZ11 registers is shown below:
The CSR controls the operation of the DZ11 and provides status information such as flags, interrupts, and maintenance.
The CSR is read/write and can be accessed as bytes or words.
The RBUF contains the received character and receive character status bits.
The RBUF is read/only and should only be accessed as a word. The RBUF register is essentially the interface to the receiver data FIFO. All of the bits in this register (except DVAL) are popped from the receiver data FIFO.
The LPR controls the UART parameters for the selected UART.
The LPR is write-only and should only be accessed as a word. This IO address is shared with the Receiver Buffer Register. A lot of the design is constrained by the COM5016 baud rate generator and the AY-5-1012 UART chip that was selected for the original DZ11.
The upper 8-bits of the TCR control the DTR signals for each line. The lower 8-bits of the TCR enable the UART transmitters for each line.
The TCR is read/write and can be accessed as bytes or words
This MSR accepts CO and RI inputs for each of the receiver lines. This register is read-only and the address is shared with the Transmit Data Register. The MSR can be accessed as either bytes or words.
Data written to the TDR is transmitted by selected transmitter UART. This register is write-only and the address is shared with the Modem Status Register. The TDR can be accessed as either bytes or words.
This section describes the DZ11 Interrupts.
A transmitter interrupt occurs when the transmitter interrupt is enabled (CSR[TIE] = 1) and the transmitter ready signal (CSR[TRDY]) transitions to asserted.
A receiver interrupt occurs under one of two mutually exclusive conditions:
If the program then dismisses the receiver interrupt, the DZ11 will interrupt when another character is available (which may be immediately if additional characters were placed in the silo while the interrupt was being serviced). Alternatively, the interrupt service routine may respond to the interrupt by emptying the silo before dismissing the interrupt.
The DZ11 is fully implemented, stable, and passes all diagnostics.
Note: The DSDZA diagnostic needs patched to in order to work correctly with the KS10 FPGA. The DSDZA diagnostic uses instruction-based timing loops for timeouts and these timeout need to be modified (increased significantly) to work with the faster FPGA implementation. Fortunately the delay count is tabularized with one entry for each baud rate. This table is called "DLYTBL:" and is at location 035650.
The diagnostic status is summarized below: