DZ11 Terminal Multiplexer - KS10FPGA/KS10FPGA GitHub Wiki

The DZ11 is an asynchronous multiplexer that provides an interface between the KS10 processor and eight asynchronous serial ports. It provides a means to control baud rate, character length, number of stop bits, parity, and transmitter/receiver interrupts for each of the eight serial ports. Lastly, the DZ11 provides some FIFO buffering (DEC called it a SILO) so that the KS10 processor did not need to service the DZ11 on every character that was received.

While this implementation of the DZ11 was designed using the Programming Manual, Technical Manual, and Users Guide; the schematics have subsequently become available. The following documenation is available:

A block diagram of the DZ11 interface is illustrated below.

The DZ11 module is fully parameterized for IO Base Address, Interrupt Number, Interrupt Vector, and supports the four device configuration. The DZ11 configuration which is documented in the Appendix B.3 of the KS10 Technical Manual and is summarized below.

DZ11 Configuration

Device

UBA

Interrupt

Interrupt
Vector

Base
Address

DZ11 #1

UBA 3

5

000340 (RX)
000344 (TX)

760010

DZ11 #2

UBA 3

5

000350 (RX)
000354 (TX)

760020

DZ11 #3

UBA 3

5

000360 (RX)
000364 (TX)

760030

DZ11 #4

UBA 3

5

000370 (RX)
000374 (TX)

760040

The KS10 FPGA currently is only configured for the DZ11 at the 3760010 IO Base Address.

Note: Although the manual mentions the IO Addresses, Interrupt, and Interrupt Vector shown in the table above; at least the DSDZA diagnostic searches for adapters at IO Addresses between 3760010 and 3762770 - which is consistent with the floating address space.

Although the DZ11 supports 8 serial interface, the KS10 FPGA IO board only provides seven TTY interfaces. The other TTY interface is tied-off internally. The 8th serial interface is used by the LP20 interface.

I have been thinking more and more about providing an alternate DZ11 design that routes the 8 TTY ports through an Ethernet interface. The DZ11 has a FIFO for the receive data which would make a clean interface between a telnet-like daemon in the console and the remainder of the DZ11 hardware. Something similar could be implemented for the transmit data.

DZ11 Register Set

The KS10 FPGA implementation of the DZ11 attempts to be register compatible with the DEC DZ11. The register interface is summarized in the following sections.

A summary of DZ11 registers is shown below:

DZ11 Register Summary

Register
Offset)

Register
Name

Access

Register Description

760010

CSR

Byte
(R/W)

Control/Status Register

760012

RBUF

Word
(RO)

Receiver Buffer Register

760012

LPR

Word
(WO)

Line Parameter Register

760014

TCR

Byte
(R/W)

Transmit Control Register

760016

MSR

Byte
(RO)

Modem Status Register

760016

TDR

Byte
(WO)

Transmitter Data Register

DZ11 Control and Status Register (CSR)

The CSR controls the operation of the DZ11 and provides status information such as flags, interrupts, and maintenance.

The CSR is read/write and can be accessed as bytes or words.

Control and Status Register

DZ11 Control/Status Register - IO Address 760010

Bit(s)

Mnemonic

R/W

Description

15

TRDY

R

Transmitter Ready

This bit is set when a line with the LINE ENB bit asserted has an empty transmit buffer

This bit is cleared by:

  1. Loading Data into the Transmitter Buffer (TDR), or
  2. Negating the line (TCR[LIN]) associated with CSR[TLINE], or
  3. Asserting Controller Clear (CSR[CLR]), or
  4. Asserting IO Bridge Clear (UBACSR[INI]).

When this bit is asserted and transmitter interrupts are enabled (CSR[TIE] = 1), a transmitter interrupt is generated.

14

TIE

R/W

Transmitter Interrupt Enable

Asserting this bit enables transmitter interrupts.

This bit is set by writing a one.

This bit is cleared by:

  1. Writing a zero, or
  2. Asserting Controller Clear (CSR[CLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

13

SA

R

Silo Alarm

This bit indicates the Receiver SILO status

This bit is asserted when the 16th character has been written into the receive FIFO.

This bit is cleared by:

  1. Reading the Receiver Buffer Register (RBUF) or
  2. Negating the Silo Alarm Enable bit (CSR[SAE]), or
  3. Asserting Controller Clear (CSR[CLR]), or
  4. Asserting IO Bridge Clear (UBACSR[INI]).

When this bit is asserted and the Silo Alarm is enabled (CSR[SAE] = 1) and receiver interrupts are enabled (CSR[RIE] = 1), a receiver interrupt is generated.

Note: The Silo Alarm (SA) is unrelated to the FIFO depth. The SA just independently counts characters. When the SA flag is asserted, the FIFO must be emptied because the SA flag will not be asserted again until another 16 characters are written to the FIFO. IOW, if you don’t empty the FIFO, the SA will be incorrect.

12

SAE

R/W

SILO Alarm Enable

This bit enables the SILO Alarm (SA) interrupt.

This bit is set by writing a one.

This bit is cleared by:

  1. Writing a zero, or
  2. Asserting Controller Clear (CSR[CLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

11

-

R

Reserved

Writes ignored.

Read as zero.

10-8

TLINE[2:0]

R

Transmit Line

When a transmitter is ready (CSR[TRDY] = 1), these bits indicate which of the transmitters can accept a character to transmit.

7

RDONE

R

Receiver Done

This bit is asserted when the Receiver FIFO is not empty.

When this bit is asserted and the SILO Alarm Interrupt is disabled (CSR[SAE] = 0) and receiver interrupts are enabled (CSR[RIE] = 1), a receiver interrupt is generated.

6

RIE

R/W

Receiver Interrupt Enable

This bit enables receiverer interrupts.

This bit is set by writing a one.

This bit is cleared by:

  1. Writing a zero, or
  2. Asserting Controller Clear (CSR[CLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

5

TIE

R/W

Master Scan Enable

This bit enables the receiver, transmitter, and FIFO

This bit is set by writing a one.

This bit is cleared by:

  1. Writing a zero, or
  2. Asserting Controller Clear (CSR[CLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

4

CLR

R/W

Controller Clear

When asserted, this bit clears the Receiver FIFO, all UARTS, and the CSR. This triggers a 15µS one-shot in the KS10.

3

MAINT

R/W

When this bit is asserted, the transmitted serial data is looped back to the receiver.

This bit is set by writing a one.

This bit is cleared by:

  1. Writing a zero, or
  2. Asserting Controller Clear (CSR[CLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

2-0

-

R

Reserved

Writes ignored.

Read as zero.

DZ11 Receiver Buffer Register (RBUF)

The RBUF contains the received character and receive character status bits.

The RBUF is read/only and should only be accessed as a word. The RBUF register is essentially the interface to the receiver data FIFO. All of the bits in this register (except DVAL) are popped from the receiver data FIFO.

Receiver Buffer Register

DZ11 Receiver Buffer Register - IO Address 760012

Bit(s)

Mnemonic

R/W

Description

15

DVAL

R

Data Valid.

This bit is asserted when there is valid data at the FIFO output. I.e., the FIFO is not empty.

14

OVRE

R

Overrun Error.

This bit is asserted when a received character has been replaced by this received character because the FIFO was full.

The FIFO overwrites the last character when the FIFO is full and a character is written.

13

FRME

R

Framing Error.

Asserted when any stop bits are missing.

12

PARE

R

Parity Error.

Asserted when parity is enabled and the received parity is incorrect.

11

-

R

Reserved.

Always read as zero.

10-8

RXLINE[2:0]

R

Received line.

This field indicates the line number of the received character.

7-0

RXCHAR[7:0]

R

Received character.

DZ11 Line Parameter Register (LPR)

The LPR controls the UART parameters for the selected UART.

The LPR is write-only and should only be accessed as a word. This IO address is shared with the Receiver Buffer Register. A lot of the design is constrained by the COM5016 baud rate generator and the AY-5-1012 UART chip that was selected for the original DZ11.

Line Parameter Register

DZ11 Line Parameter Register (LPR) - IO Address 760012

Bit(s)

Mnemonic

R/W

Description

15-13

-

W

Reserved

Writes ignored.

12

RXEN

W

Receiver clock enable.

This enables the UART receiver clock selected by LPR[LINE].

This bit is set by writing a one.

This bit is cleared by:

  1. Writing a zero, or
  2. Asserting Controller Clear (CSR[CLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

11-8

BAUD[3:0]

W

Baud rate selection.

BAUD[3:0]

Baud Rate

0000

50

0001

75

0010

110

0011

134.5

0100

150

0101

300

0110

600

0111

1200

1000

1800

1001

2000

1010

2400

1011

3600

1100

4800

1101

7200

1110

9600

1111

19200

7-6

PAR[1:0]

W

Parity selection.

PAR[1:0]

Parity

00

No parity

01

Odd parity

10

No parity

11

Even parity

5

STOP

W

Number of Stop Bits.

Stop

Number of Stop Bits.

0

1 Stop Bit

1

2 Stop Bits

4-3

LEN[1:0]

W

Character Length.

LEN[1:0]

Character Length.

00

5 bits (Baudot)

01

6 bits

10

7 bits

11

8 bits

2-0

LINE[2:0]

R

Line Number

DZ11 Transmit Control Register (TCR)

The upper 8-bits of the TCR control the DTR signals for each line. The lower 8-bits of the TCR enable the UART transmitters for each line.

The TCR is read/write and can be accessed as bytes or words

Transmit Control Register

DZ11 Transmit Control Register - IO Address 760014

Bit(s)

Mnemonic

R/W

Description

15:8

DTR[7:0]

R/W

Data Terminal Ready

These 8 registers control the state of the Data Terminal Ready (DTR) output signal for each of the 8 UARTs.

The DTR bits are asserted by writing ones.

The DTR bits are negated by:

  1. Writing zeros, or
  2. Asserting IO Bridge Clear (UBACSR[INI]).

Note: the DTR signals are implemented but are terminated (open) at the FPGA top level. The FPGA interface does not include these pins.

7:0

LIN[7:0]

R/W

Line Enable

These 8 registers control whether or not the associated UART transmitter is enabled. When enabled, an empty transmitter buffer will trigger a transmitter interrupt and/or set the CSR[TRDY] bit.

The LIN bits are asserted by writing ones.

The LIN bits are negated by:

  1. Writing zeros, or
  2. Asserting Controller Clear (CSR[CLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

DZ11 Modem Status Register (MSR)

This MSR accepts CO and RI inputs for each of the receiver lines. This register is read-only and the address is shared with the Transmit Data Register. The MSR can be accessed as either bytes or words.

Modem Status Register

DZ11 Modem Status Register - IO Address 760016

Bit(s)

Mnemonic

R/W

Description

15:8

CO[7:0]

R

Carrier Detect

These bits reflect the state of the 8 Carrier Detect (CO) signals.

Note: these signals are controlled by the DZ11 Console Control Register but are otherwise unused.

7:0

RI[7:0]

W

Ring Indication.

These bits reflect the state of the 8 Ring Indication (RI) signals.

Note: these signals are controlled by the DZ11 Console Control Register but are otherwise unused.

DZ11 Transmit Data Register (TDR)

Data written to the TDR is transmitted by selected transmitter UART. This register is write-only and the address is shared with the Modem Status Register. The TDR can be accessed as either bytes or words.

Transmit Data Register

Transmitter Data Register - IO Address 760016

Bit(s)

Mnemonic

R/W

Description

15:8

BRK[7:0]

W

Break

The BRK bits are asserted by writing ones.

The BRK bits are negated by:

  1. Writing zeros, or
  2. Asserting Controller Clear (DZCSR[CLR]), or
  3. Asserting IO Bridge Clear (UBACSR[INI]).

While a BRK bit is set, the associated line transmits zeros continuously.

7:0

TBUF[7:0]

W

Transmitter Buffer

Data written to this register is written to the UART transmitter buffer that is selected by CSR[TLINE] register bits.

DZ11 Interrupts

This section describes the DZ11 Interrupts.

DZ11 Transmitter Interrupt

A transmitter interrupt occurs when the transmitter interrupt is enabled (CSR[TIE] = 1) and the transmitter ready signal (CSR[TRDY]) transitions to asserted.

DZ11 Receiver Interrupt

A receiver interrupt occurs under one of two mutually exclusive conditions:

  1. The SILO Alarm Interrupt is disabled (CSR[SAE] = 0) and the receiver done signal (CSR[RDONE]) is asserted, or
  2. The SILO Alarm Interrupt is enabled (CSR[SAE] = 1) and the SILO alarm signal (CSR[SA]) is asserted.

If the program then dismisses the receiver interrupt, the DZ11 will interrupt when another character is available (which may be immediately if additional characters were placed in the silo while the interrupt was being serviced). Alternatively, the interrupt service routine may respond to the interrupt by emptying the silo before dismissing the interrupt.

DZ11 Status

The DZ11 is fully implemented, stable, and passes all diagnostics.

Note: The DSDZA diagnostic needs patched to in order to work correctly with the KS10 FPGA. The DSDZA diagnostic uses instruction-based timing loops for timeouts and these timeout need to be modified (increased significantly) to work with the faster FPGA implementation. Fortunately the delay count is tabularized with one entry for each baud rate. This table is called "DLYTBL:" and is at location 035650.

The diagnostic status is summarized below:

                           DIAGNOSTIC                            Result
---------------------------------------------------------------- ------
DSDZAB0 DECSYSTEM 2020 DZ11 ASYNC L MUX  . . . . . . . . . . . . Pass
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