DUP11 Bit Synchronous Serial Interface - KS10FPGA/KS10FPGA Wiki

Original URL: https://github.com/KS10FPGA/KS10FPGA/wiki/DUP11-Bit-Synchronous-Serial-Interface

The DUP11 Synchronous Serial Interface provides a relatively high speed (for the time) interface to other computers.

The DUP11 Verilog implementation is fully parameterized: the base IO address and the interrupt vector are controlled by module parameters. Two DUP11s could be instantiated and attached to the IO Bus Bridge (UBA) adapters - however only one DUP11 is currently instantiated in the code.

A summary of DUP11 registers is shown below:

Synchronous Serial Protocols

The DUP11 supports several synchronous serial protocols in hardware. This slightly lessens the CPU loading required to process these data streams.



DUP11 Registers

This section provides programming and implementation details of the DUP11 registers.

DUP11 Receiver Control/Status Register (RXCSR)

The RXCSR provides most of the control and status applicable to the serial receiver operation, including the modem control signals.

The RXCSR is read/write and is word- and byte-addressable.

DUP11 Received Data Buffer (RXDBUF)

The upper byte of this register contains the remainder of the receiver status information, including the receiver error flags. The lower bytes provides access to the Receiver Buffer Register which contains the received data.

The RXDBUF is read-only and word-addressable.

DUP11 Parameter Control/Status Register (PARCSR)

The high byte of this register contains the bits that control the DEC Mode, secondary address mode, and enable or disable the CRC logic.

The low byte (bits 0-7) contains the 8-bit secondary station address that is used only when the secondary mode is enabled in the SDLC protocol. In DEC Mode operation, this register contains the SYNC character.

The Parameter Control/Status Register is word accessible only and is write-only

DUP11 Transmitter Control/Status Register (TXCSR)

The TXCSR provides most of the control and status applicable to the transmitter operation; it also contains the bits to control the DUP11 operation in maintenance mode.

The TXCSR is read/write and is byte addressable.

DUP11 Transmitter Data Buffer (TXDBUF)

The high byte of this register contains the transmitter control and status information, plus two status bits from the Receiver CRC Register and Transmitter CRC Register.

The low byte provides the transmitter data buffer that contains the information to be transmitted.

The TXDBUF is read/write and is byte addressable.

DUP11 Interrupts

Receiver Interrupt

Transmitter Interrupt

DSDUA Transcript

A transcript of the DUP11 Diagnostic Tests is included below:

FPGA Status

The DUP11 Controller implementation is rather new and somewhat untested. The KS10 diagnostics only tests the DUP11 in SDLC mode; it does not perform any testing in DDCMP mode. The documentation for DDCMP mode is somewhat limited.

The diagnostic status is summarized below: