Console Processor - KS10FPGA/KS10FPGA Wiki

Unlike modern computers, the KS10 processor can’t actually bootstrap itself from reset without support from the console processor. Early PDP10 computers required the operator to key in the bootstrap program from the front panel interface using switches and lights. The DEC KS10 simplified the boot processes when it employed an Intel 8080 microprocessor and a board full of support circuitry to perform this function.

The KS10 Console provides boot and debug functionality to the KS10 Processor. Because of the extensive changes that are required for the KS10 FPGA implementation, the KS10 FPGA Console is significantly different than the original DEC KS10 Console and uses a more modern implementation.

Physically, the Console Processor is a Arm Cortex-A9 Hard Processor System (HPS). The HPS runs Ångström Linux and the HPS provides the following peripherals (not part of the FPGA):

The KS10 Console Interface Registers are memory mapped on the FPGA side of the AXI4-Lite HPS-to-FPGA bridge and all interactions between the KS10 Processor and the Console Processor are transacted across that bus interface.

The Console Interface Registers provide a means for the Console Processor to control the KS10 and to collect KS10 status. The Console Interface Registers also provide a means for the Console Processor to have full access to the KS10 Backplane Bus which allows the Console Processor to read and write to KS10 memory or read and write to any of the Unibus Input/Output (IO) devices.

This interface allows the Console Processor to load bootstrap executables or diagnostic executables directly into the KS10 memory.


The console hardware is fully implemented, robust, and stable. The console software is still basic but is stable and useful.

The diagnostic status of the KS10 Console is summarized below: