Signals List - ISpillMyDrink/UEFI-Repair-Guide GitHub Wiki

A few notes on some of the most important signals on any given platform, what generates them under which conditions, and how firmware is related with their (de-)assertion.

Signal names used here are taken from specifications if available, actual signal names in schematics may vary.

Disclaimer: This page requires a complete rewrite with signals being sorted by chipset generation. The current page is lacking in many regards and may confuse the reader as some signals aren't common across all generations of chipset or have slightly different functions.

Intel Platforms with Platform Controller Hub

DPWROK / DSW_PWROK (Deep Sx Well Power OK)

  • Input to the PCH
  • Assertion indicates stable Deep Sx 3.3v power rail
  • Tied to RSMRST# on platforms that don't support DeepSx
  • Assertion is necessary for completion of power up sequence (G3 to S5/S4)

APWROK (Active Sleep Well Power OK)

  • Input to the PCH
  • Assertion indicates stable ASW power rails
  • Assertion is necessary for completion of power up sequence (S5 to S0)

PWROK / PCH_PWROK (Power OK / PCH Power OK)

  • Input to the PCH
  • Assertion indicates stable PCH core power rails
  • Upon deassertion the PCH will assert PLTRST#
  • Many PCH hardstraps are sampled at rising edge (for example the Boot BIOS Straps, which select whether BIOS should be accessed from SPI, LPC, or PCI)
  • Assertion is necessary for completion of power up sequence (S5 to S0)

INTVRMEN (Internal Voltage Regulator Enable)

  • Input to the PCH, sampled at rising edge of PWROK
  • Assertion enables the internal 1.05V regulator
  • Signal must always be pulled-up to VCCRTC on desktop platforms

RSMRST# (Resume Well Reset / Primary Well Reset)

  • Input to the PCH, usually generated by the EC
  • Assertion resets the PCH's configuration registers in the suspend well
  • Deassertion indicates stable suspend plane
  • Many PCH hardstraps are sampled at rising edge
  • Bad EC (firmware) may keep this signal from deasserting
  • Deassertion is necessary for completion of power up sequence (G3 to S5/S4)
  • On mobile platforms signal often deasserts only after power button press

PLTRST# (Platform Reset)

  • Output from the PCH
  • Deassertion is necessary for completion of power up sequence (S5 to S0)
  • Corrupted Flash Descriptor may keep this signal from deasserting
  • If this signal deasserts but there is no POST, firmware is the most likely problem
  • If the CPU fails to fetch its first instruction after reset and times out, this signal is asserted

RTCRST# (RTC Reset)

  • Input to the PCH
  • Assertion resets the PCH's registers in the RTC well
  • Usually pulled up to VCCRTC
  • Deassertion is necessary for completion of power up sequence (G3 to S5)

SRTCRST# (Secondary RTC Reset)

  • Input to the PCH
  • Assertion resets the PCH's manageability registers in the RTC well
  • Usually pulled up to VCCRTC
  • Deassertion is necessary for completion of power up sequence (G3 to S5)

SYS_RESET# (System Reset)

  • Input to the PCH
  • Assertion will immediately reset the PCH

PWRBTN# (Power Button)

  • Input to the PCH, usually generated by the EC during power button press
  • Assertion for more than 4 seconds will trigger an unconditional transition to S5, followed by a transition to DeepSx on supported platforms

BATLOW# (Battery Low)

  • Input to the PCH
  • If asserted keeps the system from waking from Sx

SYS_PWROK

TODO

SLP_A# (Active Sleep Well Control)

  • Output from the PCH
  • Assertion shuts off power to all rails not required in M-Off
  • Deassertion is necessary for completion of power up sequence (S5/M-Off to S5/M3)

SLP_S0# (S0 Sleep Control) [Since 100 Series]

  • Output from the PCH, usually connected to the VRM or EC
  • Asserted when PCH is idle and CPU is in C10 state to indicate VRM may go into a light load mode

SLP_S3# (S3 Sleep Control)

  • Output from the PCH, usually connected to the EC
  • Assertion shuts off power to all rails not required in S3

SLP_S4# (S4 Sleep Control)

  • Output from the PCH, usually connected to the EC
  • Assertion shuts off power to all rails not required in S4

SLP_S5# (S5 Sleep Control)

  • Output from the PCH, usually connected to the EC
  • Assertion shuts off power to all rails not required in S5

SLP_SUS# (Deep Sx Indication)

TODO

SLP_LAN# (LAN Subsystem Sleep Control)

TODO

SLP_WLAN# (WLAN Subsystem Sleep Control)

TODO

PROCPWRGD

  • Input to the CPU
  • Assertion indicates stable VCC and VDDQ supplies

PROCHOT# (Processor Hot)

  • I/O from/to the CPU
  • Assertion by the CPU indicates that the CPU has reached its maximum safe operating temperature
  • External assertion activates the CPU's Thermal Control Circuit (TCC)

INTRUDER# (Intruder Detect)

  • Input to the PCH
  • Assertion indicates chassis opening
  • Can be set to disable the system when asserted

Intel Platforms with I/O Controller Hub

LAN_RST#

  • Deassertion is necessary for completion of power up sequence

AMD Platforms with Fusion Controller Hub

PWR_BTN# (Power Button)

TODO

SLP_S3# (S3 Sleep Power Plane Control)

  • Output from the FCH, usually connected to the EC
  • Assertion shuts off power to all rails not required in S3

SLP_S5# (S5 Sleep Power Plane Control)

  • Output from the FCH, usually connected to the EC
  • Assertion shuts off power to all rails not required in S5