Chipsets - ISpillMyDrink/UEFI-Repair-Guide GitHub Wiki

A few words on how the chipset is involved in the bring-up of the system.

Intel Platform Controller Hub

Power Planes

Processor

• Controlled by SLP_S3#

Main

• Controlled by SLP_S3#

Memory

• Controlled by SLP_S4# / SLP_S5#

Management Engine

• Controlled by SLP_A#
• Signal may be used to control ME, LAN subsytem, and SPI flash power.

LAN

• Contrlled by SLP_LAN#

Suspend Well

• Controlled by SLP_SUS#

Hard Straps

SPI Operation Voltage Select (SPIVCCIOSEL)

• Pulling this signal high will configure the SPI bus to use 1.8v logic, pulling it low will configure the SPI bus to use 3.3v logic

Boot BIOS Strap

• GPP_B22/GSPI1_MOSI on 100 Series, C230 Series, 300 Series
• Pulling this signal high will configure the PCH to read firmware from LPC, pulling it low will configure the PCH to read from SPI (Default)
• SATA1GP/GPIO19 (BBS0) and GPIO51 (BBS1) on 7 Series, 9 Series, X99 Series, C610 Series
• Pulling BBS0 and BBS1 high will configure the PCH to read firmware from SPI, pulling them low will configure the PCH to read from SPI
• Sampled at the rising edge of PWROK

Flash Descriptor Security Override (HDA_SDO)

• Pulling this signal high disables access control as defined in the Flash Descriptor and halts the Management Engine after bring up
• Sampled at the rising edge of PWROK

Boot-Block Update Scheme / Top-Block Swap

TODO

Intel Apollo Lake SoC

Hard Straps

Flash Descriptor Security Override (GPIO_118)

• Pulling this signal high disables access control as defined in the Flash Descriptor and halts the Management Engine after bring up
• Strap will be ignored if Flash Descriptor Pin-Strap Ignore soft strap has been set
• Sampled at the rising edge of RSMRST#