Bare metal C Ch06 CMSIS - Hongjayeong-02/Basic_SoC_implementation GitHub Wiki

Ch06. CMSIS

๋ชฉํ‘œ
Ch02์˜ ์ง์ ‘ ์ฃผ์†Œ/ํฌ์ธํ„ฐ ๋ฐฉ์‹์—์„œ CMSIS peripheral structure ๋ฐฉ์‹์œผ๋กœ ์ „ํ™˜ํ•œ๋‹ค.


1. CMSIS๋ž€?

CMSIS๋Š” Cortex-M ๊ธฐ๋ฐ˜ MCU software interface๋ฅผ ํ‘œ์ค€ํ™”ํ•˜๋Š” header/interface ์ฒด๊ณ„๋‹ค.

Ch02:

#define GPIOB_ODR (*(volatile unsigned int *)0x40020414UL)

Ch06:

GPIOB->ODR

๊ฐœ๋…์ ์œผ๋กœ CMSIS๋Š” peripheral register layout์„ C structure๋กœ ํ‘œํ˜„ํ•œ๋‹ค.

typedef struct
{
    volatile uint32_t MODER;
    volatile uint32_t OTYPER;
    volatile uint32_t OSPEEDR;
    volatile uint32_t PUPDR;
    volatile uint32_t IDR;
    volatile uint32_t ODR;
} GPIO_TypeDef;

๊ทธ๋ฆฌ๊ณ  base address์— structure pointer๋ฅผ ์—ฐ๊ฒฐํ•œ๋‹ค.


2. ์ง์ ‘ ์ฃผ์†Œ ๋ฐฉ์‹๊ณผ CMSIS ๋น„๊ต

ํ•ญ๋ชฉ | ์ง์ ‘ ์ฃผ์†Œ ๋ฐฉ์‹ | CMSIS -- | -- | -- Register ์ฃผ์†Œ | ์ง์ ‘ ๊ณ„์‚ฐ | Header์— ์ •์˜ ํ‘œํ˜„ | *(volatile uint32_t *)... | GPIOB->MODER Bit ์ด๋ฆ„ | ์ง์ ‘ ์ •์˜ | ST header์— ์ •์˜ ๊ฐ€๋…์„ฑ | ๋‚ฎ์Œ | ๋†’์Œ ์‹ค์ œ HW access | ๋™์ผ | ๋™์ผ

CMSIS๋„ ์—ฌ์ „ํžˆ register ์ง์ ‘ ์ ‘๊ทผ์ด๋‹ค.


3. ํ•ต์‹ฌ ๋ณ€ํ™”

RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;

์€ Ch02์˜ direct register write์™€ ๊ฐ™์€ ์˜๋ฏธ๋‹ค.


4. ์‹ค์ œ ํ”„๋กœ์ ํŠธ ๊ตฌ์กฐ

Ch06_cmsis/
โ”œโ”€โ”€ Src/
โ”‚   โ””โ”€โ”€ main.c
โ”œโ”€โ”€ Startup/
โ”‚   โ””โ”€โ”€ startup_stm32f439zitx.s
โ”œโ”€โ”€ STM32F439ZITX_FLASH.ld
โ””โ”€โ”€ STM32F439ZITX_RAM.ld

๊ณตํ†ต startup/linker/syscalls๋Š” Ch04์—์„œ ๋‹ค๋ค˜์œผ๋ฏ€๋กœ Chapter ๊ธฐ๋Šฅ ์ฝ”๋“œ์ธ main.c๋ฅผ ์•„๋ž˜์— ์ „๋ถ€ ๊ธฐ๋กํ•œ๋‹ค.


5. ์ „์ฒด ์ฝ”๋“œ

Src/main.c

/*
 * Ch06 - The Common Microcontroller Software Interface Standard (CMSIS)
 */

#include "stm32f4xx.h" /* STM32F439xx ๋งคํฌ๋กœ์— ๋”ฐ๋ผ stm32f439xx.h๋ฅผ ์ž๋™ ํฌํ•จ */

#define LD1_PIN (1UL << 0) /* PB0 = LD1 (๋…น์ƒ‰) */

static void delay(volatile unsigned int count) { while (count--) { __NOP(); } }

int main(void) { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;

GPIOB-&gt;MODER &amp;= ~(0x3UL &lt;&lt; (0 * 2));
GPIOB-&gt;MODER |=  (0x1UL &lt;&lt; (0 * 2));

while (1)
{
    GPIOB-&gt;ODR ^= LD1_PIN;
    delay(800000);
}

}


6. ์ฝ”๋“œ ํ•ด์„

Header

#include "stm32f4xx.h"

์ด header๋ฅผ ํ†ตํ•ด RCC, GPIOB, RCC_AHB1ENR_GPIOBEN, __NOP() ๋“ฑ์„ ์‚ฌ์šฉํ•  ์ˆ˜ ์žˆ๋‹ค.

GPIOB Clock Enable

RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;

PB0 Output Mode

GPIOB->MODER &= ~(0x3UL << (0 * 2));
GPIOB->MODER |=  (0x1UL << (0 * 2));

LED Toggle

GPIOB->ODR ^= LD1_PIN;

7. Ch02์™€ ๋น„๊ต

Ch02
์ฃผ์†Œ๋ฅผ ์ง์ ‘ ๊ณ„์‚ฐ
โ†“
volatile pointer ์ง์ ‘ ์ƒ์„ฑ
โ†“
register access

Ch06 CMSIS header โ†“ Peripheral structure โ†“ register access

์‹ค์ œ hardware access์˜ ์˜๋ฏธ๋Š” ๋™์ผํ•˜๋‹ค.


8. ์‹ค์Šต ๊ธฐ๋ก

Notion ๊ธฐ๋ก ๊ธฐ์ค€:

  • STM32CubeIDE CMSIS include ๊ตฌ์„ฑ

  • Build / Debug / Run

  • LD1(PB0) ์ ๋ฉธ ํ™•์ธ

  • .text = 664 bytes


9. ํ•ต์‹ฌ ์ •๋ฆฌ

  • CMSIS๋„ register-level programming์ด๋‹ค.

  • GPIOB->MODER๋Š” base address + structure member offset์œผ๋กœ ์ ‘๊ทผํ•œ๋‹ค.

  • ์ง์ ‘ pointer ๋ฐฉ์‹๋ณด๋‹ค ๊ฐ€๋…์„ฑ๊ณผ ์œ ์ง€๋ณด์ˆ˜์„ฑ์ด ์ข‹๋‹ค.

  • ์ดํ›„ Chapter๋Š” CMSIS ๊ตฌ์กฐ์ฒด ๋ฐฉ์‹์„ ๊ธฐ๋ณธ์œผ๋กœ ์‚ฌ์šฉํ•œ๋‹ค.

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