STS Register

The STS (status) register is automatically set by the CPU when it executes certain opcodes. It has 4 independed bits:

• bit 3: overflow / greater-than
• bit 2: - / equal
• bit 1: underflow / less-than
• bit 0: zero / zero

The following opcodes set the overflow, underflow and zero bits according to the value that is put into a register (note that not all of them can set all 3 bits, e.g. a ldn cannot over- or underflow):

• add, sub, mul, div, and, orr, xor, zro
• ldn, ldm, mvr, mva

The following opcodes set the greater-than, equal, less-than and zero bits according to the comparison:

• cmp

The following opcodes read the STS register:

• jmp

Note: The STS register can be read and written to like any other register, too. However, the STS bits are set after a new value is written.