BISS‐C INTRODUCTION - Hello-FPGA/BISS-C GitHub Wiki

BISS-C INTRODUCTION

BISS (Bi-Synchronous Serial interface) is a type of serial communication protocol used in sensors and actuators for high-precision measurement and control applications. It is a synchronous protocol that uses a clock signal to synchronize the data transmission between the master and slave devices. The BISS protocol has two variants: BISS-C and BISS-B. BISS-C is a unidirectional protocol used for transmitting measurement data from the slave to the master device, while BISS-B is a bidirectional protocol used for both transmitting and receiving data.

In BISS, the slave device sends a serial data stream to the master device, which includes position, velocity, or other measurement data. The master device sends a clock signal to the slave device, which uses it to synchronize the data transmission. BISS-B also includes an acknowledgment signal from the master device to the slave device to confirm that data has been received correctly.

BISS has several advantages over other serial communication protocols, including high accuracy, low latency, and high noise immunity. However, it is a complex protocol and requires specialized hardware to implement. Our IP is a FPGA logic which can communicate well with the BISS-C sensors or actuators.

1.1 DATA FORMAT AND TIMING

BiSS C-mode (unidirectional) is a fast synchronous serial interface for acquiring position data from an encoder. It is a master-slave interface. The master controls the timing of position acquisition and the data transmission speed, and the encoder is the slave. The interface consists of two unidirectional differential pairs of lines:  “MA” transmits position acquisition requests and timing information (clock) from master to encoder  “SLO” transfers position data from encoder to master, synchronized to MA.

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图 1 1 BISS-C data format

The master-slave signal communication format is RS485/RS422 differential line-driven.

A typical request cycle proceeds as follows:

  1. When idle, the master holds MA high. The encoder indicates it is ready by holding SLO high.
  2. The master requests position acquisition by starting to transmit clock pulses on MA.
  3. The encoder responds by setting SLO low on the second rising edge on MA.
  4. After the “Ack” period is complete, the encoder transmits data to the master synchronized with the clock as shown in the diagrams above.
  5. When all data has been transferred, the master stops the clock and sets MA high.
  6. If the encoder is not yet ready for the next request cycle, it sets SLO low (the Timeout period).
  7. When the encoder is ready for the next request cycle, it indicates this to the master by setting SLO high.

Description of data

  • Ack This is the period during which the valid information transmitted back.
  • Start and “0” (1 bit each) The encoder transmits the start bit to signal to the master that it is starting to transmit data. The start bit is always high and the “0” bit is always low.
  • Position (18, 26, 32 or 36 bits) The absolute position data is in binary format and sent MSB first. For rotary encoders, there are exactly 2n counts per revolution, after which the count “wraps around” to zero. [Lower resolutions may be achieved by ignoring the least significant bit(s) of the position data.]
  • Error (1 bit) The error bit is active low.
  • Warning (1 bit) The warning bit is active low.
  • CRC for position data (6 bit) The CRC polynomial for position, error and warning data is: x 6 + x1 + x 0 . It is transmitted MSB first and inverted. The start bit and “0” bit are omitted from the CRC calculation.
  • Timeout RESOLUTE encoders are capable of acquiring a new position reading every 40 µs (a maximum request cycle rate of 25 kHz). Therefore 40 µs must elapse between the start of one request cycle and the start of the next.