nf_data_sink - GregWatson/NetFPGA-PLUS-GW GitHub Wiki

Name

nf_data_sink

Version

v1.0.0

Type

IP core (HW)

Location

hw/lib/std/nf_data_sink_v1_0_0/

Interface Types

AXI4-Stream

AXI-Lite

Buses

S_AXIS: Slave AXI4-Stream bus, Variable width. The bus to be monitored.

S_AXI: Slave AXI4-Lite (for register access)

Parameters

C_M_AXIS_DATA_WIDTH: Data width of the master AXI4-Stream data bus (set to same as C_S_AXIS_DATA_WIDTH)

C_S_AXIS_DATA_WIDTH: Data width of the slave AXI4-Stream data bus.

C_M_AXIS_TUSER_WIDTH: Data width of the master TUSER bus (set to same as C_S_AXIS_TUSER_WIDTH)

C_S_AXIS_TUSER_WIDTH: Data width of the slave TUSER bus.

Register map

This module uses register infrastructure Ver 1.00, please refer to here for more details.

0x0 : ID - Block ID

0x4 : VERSION - Block Version

0x8 : RESET - Resets the registers within the nf_data_sink block

0xC : FLIP - Returns the inverted value of a written register (diagnostic)

0x10: DEBUG - Debug register, returns the written value plus a preconfigured value

0x14 : ENABLE - Enable the nf_data_sink to start capturing performance data

0x18: PKTIN - Total number of observed packets

0x1C, 0x20: BYTESIN - Total number of bytes observed. Least significant 32 bits in 0x1C.

0x24: TIME - Number of clocks over which data was measured. See later.

0x28: AXI_CLK - Free-running counter clocked by AXI clock.

0x2C: AXIS_CLK - Free-running counter clocked by AXIS clock.

Description

This block counts the number of packets and bytes transferred over the AXIS bus to which it is attached.

Operation

The block is disabled by default.

When you are ready to start counting data then enable this block (ENABLE)

NOTE: the block does not start any counters until it sees the first activity after it is enabled.

The block will continue to count the number of packets and bytes until it is disabled. The timer counter (TIME) counts the number of clocks from the first active data transaction on the bus until the last active transaction on the bus (end of packet).

So if you enable the block, send 1 packet of data seen at clock count T0, then later send a second packet for which the last bus transaction occurs at clock count T1 then the TIME count will be the value T1-T0. If you then send a third at T2 then the TIME counter will be updated to be T2-T0.

Sampling the counters

In order to obtain an accurate measurement, all of the counters must be sampled at the same time. Software must issue a sample command to the block before reading the counters.

So the sequence of operations is:

  1. Write 1 to the ENABLE register
  2. Start sending packet data
  3. Sample the performance data at any time and continue counting:
  • Write 3 to the ENABLE register (write 1 to bits 0 and 1). This samples the counters but does not interrupt counting.
  • Read the PKTIN, BYTESIN, and TIME counters. These will all have been sampled at the same clock.
  • Repeat from 3. as needed.
  1. Write 0 to ENABLE to disable the block and reset all registers.

NOTE The nf_data_sink block must receive at least one packet before you can sample the registers.

Sample application

The pkt_send application uses this block. See sw/app/pkt_send.