SPI is an acronym for (Serial Peripheral Interface) pronounced as “S-P-I” or “Spy”. Which is an interface bus typically used for serial communication between microcomputer systems and other devices, memories, and sensors. Usually used to interface Flash Memories, ADC, DAC, RTC, LCD, SDcards, and much more. The SPI was originally developed by Motorola back in the 80s to provide full-duplex serial communication to be used in embedded systems applications.

In typical SPI communication, there should be at least 2 devices attached to the SPI bus. One of them should be the master and the other will essentially be a slave. The master initiates communication by generating a serial clock signal to shift a data frame out, at the same time serial data is being shifted-in to the master. This process is the same whether it’s a read or write operation.

• MOSI -> Master output slave input (DOUT From Master).
• MISO -> Master input slave output (DOUT From Slave).
• SCLK -> Serial Clock, generated by the master and goes to the slave.
• SS -> Slave Select. Generated by the master to control which slave to talk to. It’s usually an active-low signal.

Other naming conventions are followed by different manufacturers across the globe. But in the end, they are referring to the same things. Here are some of the commonly used terms to express the above 4 logic lines (SPI Bus).

MISO (master in slave out) => can also be SIMO, DOUT, DO, SDO, or SO (At The Master End).

MOSI (master out slave in) => can also be SOMI, DIN, DI, SDI, or SI (At The Master End).

SS (slave select) => can also be CE, CS, or SSEL.

SCLK (serial clock) => can also be SCK.

The convention we’re going to follow in this tutorial and upcoming topics related to SPI will be the following one

[ SDI, SDO, SCK, SS]

The typical SPI connection between a single master and a single slave is indicated in the diagram below.

Devices on the SPI bus can operate in either mode of the following: Master or Slave. There must be at least one master who initiates the serial communication process (For Reading/Writing). On the other hand, there can be single or multiple devices operating in slave mode.

The master device can select which slave to talk to by setting the SS (slave select) pin to logic low. If a single slave is being addressed, you can tie the SS pin of this slave device to logic low without the need to control this line by the master.

The Master device on the SPI bus has to configure and generate the clock signal at the beginning of any communication. During each SPI clock cycle, full-duplex data transmission occurs. The master sends a bit on the MOSI line and the slave reads it, while the slave sends a bit on the MISO line and the master reads it.

This sequence is maintained even when only one-directional data transfer is intended. Which means in order to receive any data you have to actually send something! in this case, we call it “Dummy Data” or “Junk”!

Theoretically, the clock rate can be whatever you want provided that it’s practically realizable. The SPI serial clock is derived from the CLKsys of your system, which means it can by Fosc/2 or 4, 8, 16 or whatever. The dynamic range starts from a few KHz up to several MHz. (Practical limitations are case-dependent for each system).

Besides configuring the serial clock rate (frequency), the SPI Master device should also configure the clock polarity. The clock polarity is usually written as CKP or CPOL depending on the hardware manufacturer but in the end, it’s the same. The clock polarity & phase together determine when will the data be latched on the data line.

CKP can be configured to be 1 or 0. Which means you can set the default state of the clock (the IDLE) to be high or low whichever you want. The polarity inversion can be achieved by a simple logic inverter. You have to refer to the device’s datasheet in order to set both CKP & CKE properly.

• For (CKP = 0), the clock IDLEs at 0, and each cycle consists of a pulse of 1. That is, the leading edge is a rising edge, and the trailing edge is a falling edge.
• For (CKP = 1), the clock IDLEs at 1, and each cycle consists of a pulse of 0. That is, the leading edge is a falling edge, and the trailing edge is a rising edge.

Besides configuring the serial clock rate and polarity, the SPI Master device should also configure the clock phase (or Edge). The clock phase is usually written as CKE or CPHA depending on the hardware manufacturer but in the end, it’s the same. The clock polarity & phase together determine when will the data be latched on the data line.

CKE can be configured to be 1 or 0. Which means you can set the edge on which the data will be latched whether it’s a rising or falling edge (leading or trailing). You have to refer to the device’s datasheet in order to set both CKP & CKE properly.

• For (CKE = 0), the “out” side changes the data on the trailing edge of the preceding clock cycle, while the “in” side captures the data on (or shortly after) the leading edge of the clock cycle.
• For (CKE = 1), the “out” side changes the data on the leading edge of the current clock cycle, while the “in” side captures the data on (or shortly after) the trailing edge of the clock cycle.

The clock phase and the polarity together control whether the data is latched on the rising or falling edge (CKE) as well as the IDLE state of the clock (CKP). The diagram below summarizes all the clock configuration combinations and highlighting when the data is actually latched.

As you might have noticed, if the SPI Master doesn’t configure the CKP (clock polarity) & CKE (clock phase) to what the slave device expects, any sort of communication (write/read) will fail.

The combination of both clock polarity and phase is commonly referred to as “SPI Mode”. All the possible modes are numbered following the convention down below.

SPI Mode	Clock Polarity(CKP/CPOL)	Clock Phase(CPHA)	Clock Edge(CKE/NCPHA)
0    [00]	0	0	1
1    [01]	0	1	0
2    [10]	1	0	1
3    [11]	1	1	0

[Note that: NCPHA is the inversion of CPHA signal]. The above table shows the SPI mode numbers for Microchip PIC and ARM-Core Based Microcontrollers. Other microcontrollers follow the convention below

SPI Mode	CPOL	CPHA
0    [00]	0	0
1    [01]	0	1
2    [10]	1	0
3    [11]	1	1

You should also double-check the modes table included in the microcontroller’s datasheet to make sure everything is OK.

All devices on the SPI bus including the master and all slaves can all be connected in a couple of different configurations. Which mostly depend on how they are manufactured and how data should be flowing through the network of devices in that particular application. I’ll briefly describe both of these configurations hereafter.

Daisy Chain

In the digital communication world, when devices are connected together in such a way that data has to circulate between devices until it reaches destination device, it’s then called a Daisy Chain!

Each device is connected between 2 other devices in a circular (Logically) way as shown in the diagram down below. [note that: a logical circle is a term that describes data circulation flow in the network which means that devices connection doesn’t necessarily need to be circular in shape].

The SPI port of each slave device is designed to send data out during the second group of clock pulses an exact copy of the data it received during the first group of clock pulses. The whole chain acts as a communication shift register. Each slave copies the input data to the output in the next clock cycle until the SS line goes high. Such a feature only requires a single SS line from the master, rather than a separate SS line for each slave.

That means a data frame will keep propagating through slave devices as long as the SS line is held low. The following diagram will show you how a single SPI master can address multiple slave devices using only one SS line.

And that’s it for the daisy chain SPI bus configuration. Now, we’ll turn over to see the other configuration which we’ll be actually implementing before the end of this tutorial.

In the independent slave configuration, there is an independent slave select line for each slave. This is the way SPI is normally used. The master asserts only one chip select at a time. Since the SDO/SDI pins of the slaves are connected together, they are required to be tri-state logic pins. Slave devices which don’t support tri-state may be used in independent slave configuration by adding a tri-state buffer chip controlled by the chip select signal.

A typical connection diagram for a system with multiple slaves connected in the independent configuration is shown below.

As you can see, this configuration can be impractical in case your system involves many SPI slave devices. Which will require too many IO pins to control all SS lines.

There are many reasons that make SPI stands out as a serial communication interface. Here is a short list for the pros of SPI.

• Full-Duplex serial communication.
• Potentially high-speed data transfer rates can be achieved with SPI.
• Few wires are required for the SPI Bus (typically 4 lines).
• Easy software configuration and setup.
• Extremely flexible data transfer. It’s not limited to 8-Bits, it can be any arbitrarily-sized words.
• Very simple hardware structure. Slaves don’t need unique addresses (unlike I2C). Slaves use the master’s clock and do not need precision oscillators (unlike UART). Transceivers are not needed (unlike CAN).

• No hardware slave acknowledgment (the master could be transmitting to nowhere without knowing).
• Typically supports only one master device.
• Requires more pins (unlike I2C).
• No hardware-level error-checking protocol is defined.
• Many existing variations and conventions make it ambiguous sometimes and you’ve to dig very deep in the datasheet and underline every single word.
• Can only support very short distances (usually onboard communications) compared to RS-232 and CAN-Bus.