This workspace is organized for modular VHDL development. To create a new project, follow these steps

• Navigate to src/Template_Project/.
• Copy the entire Template_Project folder.
• Rename the copied folder to your new project name (e.g., <your_module>).

• Open the new project’s Makefile.
• Change PROJ variable from Template_Project to module name <your_module>.

• Rename template.vhd to <your_module>.vhd.
• Rename tb_template.vhd to tb_<your_module>.vhd.

• Implement your logic in <your_module>.vhd.
• Update the testbench (tb_<your_module>.vhd) to test your new module.

• Use the provided commands to compile and simulate your design.
• Available commands are,
  • make – builds the project.
  • make run – build the project and run in GTKWave.
  • make clean – clean the artifacts.

Each project folder should contain

• Makefile
• <module>.vhd (your VHDL source)
• tb_<module>.vhd (your testbench)

1. Copy and rename

   cp -r src/Template_Project src/My_New_Gate
   mv src/My_New_Gate/template.vhd src/My_New_Gate/My_New_Gate.vhd
   mv src/My_New_Gate/tb_template.vhd src/My_New_Gate/tb_My_New_Gate.vhd

2. Edit Makefile and VHDL files as described above.

src/
  My_New_Gate/
    Makefile
    My_New_Gate.vhd
    tb_My_New_Gate.vhd