Architecture Design - EML-Labs/PPG-Peak-Detection-on-FPGA GitHub Wiki

Architecture Design

Block Diagram

flowchart TD
    %% Subgraph: Signal Acquisition
    subgraph Signal Acquisition
        A1[I²C Master MAX30102]
        A2[PPG Sample Buffer]
        A1 --> A2
    end

    %% Subgraph: Preprocessing Block
    subgraph Preprocessing_Block
        P1[Preprocessing Filter<br/>- Noise removal<br/>- Baseline correction<br/>- Smoothing]
    end

    %% Subgraph: Feature Extraction
    subgraph Feature_Extraction
        F1[Peak Detector<br/>- Detect PPG peaks]
        F2[PPI Calculator<br/>- Calculate Inter-Beat Intervals]
        F1 --> F2
    end

    %% Subgraph: Computation and Output
    subgraph Computation_and_Output
        C1[HRV Metrics<br/>- SDNN, RMSSD, pNN50, etc.]
        C2[Output Interface<br/>- Display / UART / BLE]
        C1 --> C2
    end

    %% Data Flow Connections
    A2 --> Preprocessing_Block --> Feature_Extraction --> Computation_and_Output
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1. Signal Acquisition

  • Interface: I²C Master FSM with INT-trigger from MAX30102.
  • Each interrupt triggers a read from FIFO (FIFO_DATA register).
  • Collected 24-bit Red/IR PPG samples.
  • Buffers data into FIFO (BRAM or shift register).

2. Preprocessing Block

  • Noise removal,
    • Low-pass FIR/IIR (cutoff ~10 Hz) to remove high-frequency noise.
    • Optional high-pass to remove baseline drift.
  • Implemented as pipelined FIR filters in HDL or Xilinx FIR IP Core.
  • Output = clean PPG waveform.

3. Feature Extraction

  • Detect systolic peaks using,

    • Derivative sign change (slope + → –).
    • Threshold check (adaptive or fixed).
    • Refractory logic (≥250 ms between peaks).

  • Outputs peak_flag = 1 for one clock when heartbeat detected.

  • Counts clock cycles (or sample intervals) between peaks.

  • Stores result in register/FIFO.

  • Output = PPI value in samples → later converted to ms.

4. Computation & Output

  • Time-domain HRV metrics,

    • Mean RR (avg interval)
    • SDNN (std deviation of intervals)
    • RMSSD (root mean square of successive diffs)

  • Simple DSP arithmetic units (adders, subtractors, multipliers, dividers).

  • Can use pipelined fixed-point arithmetic for FPGA efficiency.

  • Use Output interface like,

    • UART → PC for logging.
    • AXI Bus → SoC / MicroBlaze for further processing.
    • On-board Display → LEDs or 7-seg show heart rate.

Control & Data Flow

  • Control Path - FSMs (I²C, Peak Detector, Refractory Counter).
  • Data Path - PPG samples flow through filters => peak logic => interval calculator => HRV stats.
  • Synchronization - All modules clocked by FPGA system clk
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