TileLink - EECS-NTNU/rocket-chip GitHub Wiki

links

• rocket-chip-read
• talk on tilelink - slides
• paper on tilelink and diplomacy
• tilelink spec

protocol

• 5 channels a-e
• a is lowest priority, e highest
• used as a cache coherent memory access protocol
• message based
• uses decoupled ready valid interface
• not part of io but separate
• example from ICache

  val (tl_out, edge_out) = outer.masterNode.out(0)             //master port
  val (tl_in, edge_in) = outer.slaveNode.in.headOption.unzip   //slave port (unused and not present)