exisiting projects

• https://github.com/ucb-bar/fpga-zynq - original zynq repository
• https://www.lowrisc.org/docs/refresh-v0.6/ - modified (sv shell?) rocket running on zynq
• https://github.com/sifive/freedom - supports virtex 7 and atrix 7
• https://github.com/cnrv/fpga-rocket-chip -seems to have a good description of the whole boot process

parallella-riscv

• https://github.com/eliaskousk/parallella-riscv
• updated for zynq
• zedboard & parallella
• apparently rocket changed from using HTIF to new debug protocol - making new versions incompatible
  • why could it be updated in 2018?? New fesvr version??

changes needed for pynq

linux image??

uboot??

bitstream??

versions used

• rocket: 04.2018
• testchipip: 04.2018

PYNQ-Z1 docu

• https://reference.digilentinc.com/reference/programmable-logic/pynq-z1/reference-manual#basic_io
• Arty Z7-20 - mostly the same but better docu (e.g. vivado boardfiles) - https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start

Alternative

• build simple system with only uart, jtag and axi-ram

Advantages:

• jtag seems to be using the new debugging interface => possibly able to track rocket repository
• no need to deal with linux on zynq - only uboot necessary for ram
• uart and jtag should be mappable to gpio - use external jtag tool for debugging
• might be less work than figuring out how to deal with all the deprecated stuff needed for fesvr

Things to figure out:

Is booting over jtag possible??

• probably - since afaik the emulator uses same interface to load binaries ##TODO checklist
• build minimal rocket config using diplomacy
  • done TODO: handle jtag tdo tristate??
• build minimal vivado project that has access to ram
  • adjusting the existing design
    • connect reset to jtag_reset?
  • had to modify vivado init script to use US number format to get clock to work: https://www.xilinx.com/support/answers/53090.html /home/david/Xilinx/Vivado/2019.1/scripts/Vivado_init.tcl
• find/build suitable uboot image
  • http://adiuvoengineering.com/microzed-chronicles/
  • https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/A-Boot-Loader-for-MicroZed-Adam-Taylor-s-MicroZed-Chronicles/ba-p/378855
  • https://www.xilinx.com/html_docs/xilinx2018_1/SDK_Doc/SDK_concepts/concept_fsbl_parameters.html
  • https://www.xilinx.com/html_docs/xilinx2018_1/SDK_Doc/SDK_tasks/task_creatinganewzynqfsblapplicationproject.html
  • https://www.xilinx.com/html_docs/xilinx2018_1/SDK_Doc/SDK_tasks/task_creatingabootimage.html
  • https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug1165-zynq-embedded-design-tutorial.pdf
  • if using linux:
    • https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841683/Linux+Reserved+Memory Arty BSP:
    • https://github.com/Digilent/Petalinux-Arty-Z7-20
  • https://www.centennialsoftwaresolutions.com/post/bare-metal-application-boot-from-flash-on-the-xilinx-zynq-7000-of-the-zc702
  • https://forums.xilinx.com/t5/Processor-System-Design/PYNQ-Z1-Bootloader-Bin-QSPI-SD-Generation-Boot-Not-Working/td-p/737750
  • http://svenand.blogdrives.com/archive/201.html
• modify bootrom to start into debug mode??
  • uart output in bootloader??
• figure out how to debug using jtag
  • openocd??
    • basic procedure: https://github.com/riscv/riscv-isa-sim
  • try it using emulator with suitable config
    • described in https://github.com/chipsalliance/rocket-chip/issues/1339
• step by step instructions:
  • generate verilog
  • generate bitstream
  • flash bitstream
  • connect jtag
  • start openocd
    • ~/git/freedom/builds/NtnuRocketZynq/openocd/openocd$ sudo $RISCV/bin/openocd -f jtag.cfg
  • start gdb
    • ~/git/freedom/builds/NtnuRocketZynq/openocd$ $RISCV/bin/riscv64-unknown-elf-gdb xip.elf
    • set remotetimeout 2000
    • target remote localhost:3333
  • load desired elf file
• ???
• profit

freedom zybo

• seems to work

JTAG connection

JTAG signal	ftdi 2232H Pin	PYNQ-Z1 Pin	ZYNQ Pin	color
GND	GND	GND	GND	brown
JTAG_TCK	AD0	IO37?	Y7	orange
JTAG_TMS	AD3	IO1	U12	blue
JTAG_TDI	AD1	IO2	U13	yellow
JTAG_TDO_data	AD2	IO3	V13	green
JTAG_TDO_driven	-	IO4	V15	-
JTAG_reset	AC2	IO5	T15	purple
UART_txd		IO6	R16
UART_rxd		IO7	U17

https://www.instructables.com/id/ESP32-Cheap-Solution-for-in-Circruit-Debug/