Over the past several decades, engineers have been at the forefront of innovation, working to bring forth cutting-edge technologies such as AI, autonomous vehicles, and smartphones. These advanced products are heavily reliant on semiconductors, which play a critical role in powering complex computations and improving overall performance by speeding the movement of data. Without high-quality chips, these systems would not function optimally. In other words, the semiconductor industry is the fundamental industry that can help engineers accomplish their goals. However, the front-end process of semiconductor manufacturing is expected to reach its limits. The industry analyzed that the micro-process competition has reached its limit due to technical problems such as quantum tunneling. To improve the quality of the semiconductor, the development of the back-end process becomes essential and packaging is the key to this back-end process. Before the introduction to packaging, an understanding of the overall manufacturing process is needed. Samsung and ASML, semiconductor manufacturing companies, introduced the eight main steps of making semiconductors from sand.

<Fig 1. Semiconductor Manufacturing Process>

The first step is the extraction of the ingot, a large circular pillar made of silicon which is the main ingredient of semiconductors due to its electrical properties. The ingot is then sliced into wafers, which will be given a protective layer of SiO2. Next, tiny circuits are drawn on the wafers at a scale of nanometers and the material is ionized to enhance its electrical properties. These wafers are then cut into even smaller chips, and these steps are considered as front-end processes. The final step in the process is packaging, which serves to protect the chip from external damage, check its electrical performance, and meet dimensional requirements (Timings, 2021).

Why packaging has become so important nowadays?

Packaging has become increasingly important recently due to advancements in technology. With the development of complex computations and larger batteries, there is a growing need for more components in products. For example, companies have started to explore innovative methods of chip stacking and arrangement, in order to save space and reduce energy waste. In the 1970s, the traditional single-die packaging method, which consisted of a single die in a package, was widely used. However, as society demanded more functionality in smaller spaces, engineers developed the System on Chip (SoC) technology. This innovative solution embeds the entire system on a single chip and has become a widely adopted method in the industry, such as Qualcomm Snapdragon. SoC not only reduces the space required for the system but also reduces energy waste and costs. The reduction of energy was possible because engineers could downsize the multi-chip designs to a single chip. This downsize had another positive effect of securing space in the device and making the size of the device itself smaller.

<Fig 2. Image of System on Chip from Physical Design for 3D System on Package>

What is the current technology? With numerous companies competing to develop cutting-edge packaging technologies, there are now various types of packaging available. One that has made remarkable advancements in this field is Taiwan Semiconductor Manufacturing Company (TSMC). TSMC has achieved great success by incorporating Fan-out Wafer Level Packaging (FOWLP) technologies into its products. To understand the significance of this technology, it's important to know about Wafer-Level Packaging. Unlike the traditional method, where the packaging was done after cutting the wafer into chips, Wafer-Level Packaging involves applying the packaging on the entire wafer before cutting it into individual chips. This approach has two key advantages - improved signal integrity and the ability to carry out reliability and testing processes at the wafer level.

<Fig 3. Comparison of traditional packaging and Wafer-Level Packaging>

Fan-Out Wafer Level Packaging (FOWLP) is one of the Wafer-Level Packaging types. This FOWLP becomes more attractive since it has the key advantages of Wafer-Level Packaging and flexible integration on diverse devices is possible after the thermal process. The experiment which was progressed at Nanyang Technological University showed the thermal test effect on FOWLP. The study showed that the flexure strength of FOWLP increased significantly after the thermal process.

<Fig 4. Flexure Strength before and after the thermal process>

Hence, this technology can prevent the chip from cracking due to the outsourcing impact.

The semiconductor industry has played a significant role in driving innovation and technological advancements over the past several decades. As the front-end process of semiconductor manufacturing reaches its limits, the development of the back-end process, particularly packaging, becomes increasingly important. With the demand for more components in smaller spaces, companies have explored innovative packaging methods, such as System on Chip (SoC) technology and Fan-Out Wafer Level Packaging (FOWLP), which have revolutionized the industry. The advantages of FOWLP, such as improved signal integrity and reliability, have made it an attractive option for semiconductor manufacturers like TSMC. As technology continues to evolve, it's clear that packaging will continue to be a critical component in the production of high-quality chips. Advancements in packaging technology will likely play a crucial role in enabling the development of smaller, more powerful, and more energy-efficient devices, making it a key area of focus for the industry going forward.

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Lim, Sung Kyu. (2005, June) Physical Design for 3D Systems on Package. ResearchGate. Retrieved 10 Feb. 2023 from https://www.researchgate.net/publication/264591143_Physical_Design_for_3D_System_on_Package

Samsung Electronics (2022, Nov 15) Semiconductor Packaging Explained | All about Semiconductors. Retrieved 9 Feb. 2023 from https://www.youtube.com/watch?v=7gg2eVVayA4

Timings, Jessica (2000, Oct 6) 6 crucial steps in semiconductor manufacturing. Retrieved 9 Feb. 2023 from https://www.asml.com/en/news/stories/2021/semiconductor-manufacturing-process-steps

Xu, Cheng; Zhoung, Zhao Wei; Choi, W.K (2017 May 8). Effect of high temperature storage on fan-out wafer level package strength. IEEE. Retrieved Mar 24 from https://ieeexplore.ieee.org/abstract/document/7919844?casa_token=LSM_ciYcPEQAAAAA:Mn2HPdc1WxK362W1BcBulLaz7IwDP7JFFplsd-6jz7cJ2JvO25oqnNJj6EIAuxfV0DeSg2I6z7g