• The virtual interface is a variable that represent the interface instance.

• The virtual interface is used to create a interface instance in the class because the interface is a static component and the system verilog test bench is a dynamic component. we cannot directly declare the interface in the class by using the variable virtual we can declare the interface instance in the class

  synatax: virtual interface_name instance_name;

interface_name: name of the interface
instance_name: name of the interface instance can be called in the class with variables Ex: vif.variable;

• The virtual interface must be initialized in the class pointing to actual interface. Declaration of virtual interface in the class `Example: Virtual intf vif;

• Accessing of uninitialized virtual interface result in fatal error.

• The virtual interface can be passed as argument to the task and function methods.

• The virtual interface can be a property of class and which is initialized by using the function argument i.e it can call the actual interface in the particular class and create the instance of interface in that class

  Example: function new(virtual intf vif);

• The virtual interface can be passed as argument to the function methods Calling the actual interface 'intf' to declare the virtual interface in the class using the procedure or in function argument by using new() construct.

• The interface variables can be accessed by virtual interface handles inside the class function and task methods as virtual_instance_name.variable;

Example : vif.a

vif is a virtual_instance_name;
a is the variable/property of class

• The keyword/signal virtual interface variable represent the different interface instance in different time through out the simulation time

    syntax: interface <interface_name>();  
           <port_list>;  
            ..........  
            endmodule  
       To connect static(interface module) to   
       to dynamic(class) we use virtual interface  
        class clase_name;
         virtual <interface_name> <interface_instance>;
         .......
       properties;
         .....
       function()
        .....
      endfunction    
        task();
         ......
         endtask
         endclass
  

Example1: Fulladder

Interface module of full adder

`interface adder();
 logic in_a,in_b,in_c;
  logic out_sum,out_carry;
 endinterface

Virtual Interface declaration inside the class

  `//class:driver.sv
    class driver;

   //Declaration of virtual interface
   //syntax: virtual interface_name interface_instance;
   virtual adder vif;

   //constructor
   function new(virtual adder vif);
    //this.vif refer to class driver
   //vif refer to the function argument
   this.vif = vif;

 endfunction
//task
 task run();

   repeat(10) begin
  //interface_instance.variable
  vif.in_a = $random;
  vif.in_b = $random;
   vif.in_c = $random;
   $display("");
   $display("//INPUT:Values  \n a=%0b, b=%0b, cin =%0b", vif.in_a,vif.in_b, vif.in_c);
    #5;
   $display("");
  $display("//OUTPUT: \n sum=%0b, carry = %0b\n", vif.out_sum, vif.out_carry);

end

endtask endclass

Top module of full adder

  //including the test.sv and interface.sv files
`include "test.sv"
`include "interface.sv"

 //module:top
 module top;
//creating  an instance of interface
 adder intf();

// the instance of test  t1.
 test t1(intf);

//fulladder DUT instance , connecting the interface signal to instance DUT
fulladder dut(.in_a(intf.in_a), .in_b(intf.in_b), .in_c(intf.in_c), .out_sum    (intf.out_sum), .out_carry(intf.out_carry));
endmodule

Below figure shows the design block of the code:

                                 Fig.1: Design Block diagram

Here in the Figure:1, the driver is a class here we declare the virtual interface because inside the class we cannot call the interface directly because interface is static component and class is dynamic component. so this virtual keyword is used to create the instance in the class (it will create the memory space) inside the class. In driver we generates the random stimulus and send to the interface, the DUT signals are connected to interface. The DUT output is given to the interface the test block consist of class and the top module consist of all the component such as test, interface and DUT the instance of all component is created in the Top module/block.

Below figure shows the output of full adder:
Here in the Figure.2 shows the output of full adder where a, b & cin are the input of the full adder, sum and carry are the output of the fulladder

                     Fig: Output of Full adder 

![and gate])![and gate])![and gate])![and gate])![and gate])![and gate])