clocking block - DilipKrishnappa/interface GitHub Wiki

clocking block

Example D_flipflop

clocking block

Clocking Skew

The below figure shows the Input skew and output skew

image

                                     Fig 2: Input skew and output skew

Input signals are sampling with respect to the clock event. If an input skew is specified then the signal is sampled at skew time units before the clock event. Then the output signals are driving skew simulation time units after the corresponding clock event. Input skew is implicitly negative because it happens before the clock.

In Input skew, the input signal sampled at the end of previous step ie, postponed region and output signal sampled at after some time corresponding to their clock event ie, Observed Region. In Output skew is positive because it refers the time after the clock event.

Eg. default input #3ps output #2

Syntax

clocking cb @(posedge clk);
default input #1step output #0;
input from_Dut;
output to_Dut;
endclocking

CASE : 1

posedge_df_cb

In this case both DUT (clocking block clock) and Test is triggered at positive edge (interface clock).
Here in this scenario, the wave form output and display statement output is mismatching.
the output is shown in the below figure

Example code:

DUT code:

 // module:d_flipflop   
 module d_flipflop(dff.dut intf);  

  //clocking block cd  
  always @(intf.cd)  

 //Non-Blocking assignment   
 intf.cd.q <= intf.cd.d;  

  endmodule : d_flipflop

Interface code:

 //module: Interface  
 interface dff(input clk);    

//declare the signals    
logic d;   
logic q;   

 //Clocking block for dut    
 clocking cd @(posedge clk);   
  default input #1step output #0;   
    output q;   
     input d;    
   endclocking     

//modport for dut    
  modport dut(clocking cd);    

//modport for tb     
modport tb(input q, output d, input clk);`   

 endinterface: dff

Test code:

 //module: test
  module test(dff.tb intf);

  //task:drv
  task drv;

//loop
repeat(10)
  begin
//test triggering at posedge
    @(posedge intf.clk )

//randomzing the d
   
intf.d <= $random;
 $display("test side[%0t]=d_tb_drive:%d q_dut_sample:%d",$time,intf.d, intf.q);
  end
  $finish;
 endtask 

 //calling the task drv
 initial
   begin
   drv();
   end 
 endmodule :test

Top module

 //including the file test.sv and interface.sv  
  
     `include "test.sv"      
     `include "interface.sv"    

 module top;
  
 bit clk=1;

 initial
forever #5 clk = ~clk;

 //creating interface instance
   dff intf(clk);

 //d_flipflop instance
  d_flipflop t1(intf);  

//test Instance
 test t2(intf);

 initial
 $monitor("DUT side [%0t]=d_tb_drive:%d q_dut_sample:%d",$time,intf.cd.d, intf.cd.q);
  endmodule : top

Transcript output

dff_cb_ss4

output of d_ff for all clock cycles

dff_cb_ss3

CASE : 2

negedge_dff_cb

In this case both DUT is triggered at negative edge (clocking block clock) and Test is triggered at positive edge (same interface clock).
Here in this scenario, the wave form output is mismatching with respect to the test(tb) and DUT waveform is matching, display statement output is matching.
the output is shown in the below figure

Example code:

DUT code:

 // module:d_flipflop   
 module d_flipflop(dff.dut intf);  

  //clocking block cd  
  always @(intf.cd)  

 //Non-Blocking assignment   
 intf.cd.q <= intf.cd.d;  

  endmodule : d_flipflop

Interface code:

 //module: Interface  
 interface dff(input clk);    

//declare the signals    
logic d;   
logic q;   

 //Clocking block for dut    
 clocking cd @(negedge clk);   
  default input #1step output #0;   
    output q;   
     input d;    
   endclocking     

//modport for dut    
  modport dut(clocking cd);    

//modport for tb     
modport tb(input q, output d, input clk);`   

 endinterface: dff

Test code:

 //module: test
  module test(dff.tb intf);

  //task:drv
  task drv;

//loop
repeat(10)
  begin
//test triggering at posedge
    @(posedge intf.clk )

//randomzing the d
   
intf.d <= $random;
 $display("test side[%0t]=d_tb_drive:%d q_dut_sample:%d",$time,intf.d, intf.q);
  end
  $finish;
 endtask 

 //calling the task drv
 initial
   begin
   drv();
   end 
 endmodule :test

Top module

 //including the file test.sv and interface.sv  
  
     `include "test.sv"      
     `include "interface.sv"    

 module top;
  
 bit clk=1;

 initial
forever #5 clk = ~clk;

 //creating interface instance
   dff intf(clk);

 //d_flipflop instance
  d_flipflop t1(intf);  

//test Instance
 test t2(intf);

 initial
 $monitor("DUT side [%0t]=d_tb_drive:%d q_dut_sample:%d",$time,intf.cd.d, intf.cd.q);
  endmodule : top

Transcript output

dff_cb_ss2

output of d_ff for all clock cycles

dff_cb_ss3

CASE : 3

In this case both DUT is triggered at negative edge (clocking block clock) and Test is triggered at positive edge (interface clock).
Here in this scenario, the wave form output DUT and Tb is matching and display statement output is matching.
here we randomizing the value of 'd' after some delay time, so that the waveform is matching in this case-3 compared to case-2
the output is shown in the below figure

Example code:

DUT code:

 // module:d_flipflop   
 module d_flipflop(dff.dut intf);  

  //clocking block cd  
  always @(intf.cd)  

 //Non-Blocking assignment   
 intf.cd.q <= intf.cd.d;  

  endmodule : d_flipflop

Interface code:

 //module: Interface  
 interface dff(input clk);    

//declare the signals    
logic d;   
logic q;   

 //Clocking block for dut    
 clocking cd @(negedge clk);   
  default input #1step output #0;   
    output q;   
     input d;    
   endclocking     

//modport for dut    
  modport dut(clocking cd);    

//modport for tb     
modport tb(input q, output d, input clk);`   

 endinterface: dff

Test code:

 //module: test
  module test(dff.tb intf);

  //task:drv
  task drv;

//loop
repeat(10)
  begin
//test triggering at posedge
    @(posedge intf.clk )


//randomzing the d
   #3ns;
intf.d <= $random;
 $display("test side[%0t]=d_tb_drive:%d q_dut_sample:%d",$time,intf.d, intf.q);
  end
  $finish;
 endtask 

 //calling the task drv
 initial
   begin
   drv();
   end 
 endmodule :test

Top module

 //including the file test.sv and interface.sv  
  
     `include "test.sv"      
     `include "interface.sv"    

 module top;
  
 bit clk=1;

 initial
forever #5 clk = ~clk;

 //creating interface instance
   dff intf(clk);

 //d_flipflop instance
  d_flipflop t1(intf);  

//test Instance
 test t2(intf);

 initial
 $monitor("DUT side [%0t]=d_tb_drive:%d q_dut_sample:%d",$time,intf.cd.d, intf.cd.q);
  endmodule : top

Here the DUT trigger at the negative edge clock and test triggered at the positive edge clock.
The test(Tb) drive the random values 'd' to the DUT. the DUT sample the value and drive the 'q' to the Tb

**1st duty cycle @(negedge dut & posedge test) **
The 1-duty cycle is 10ns. Initially the D_flipflop value are indeterministic state i.e d=1'dx and q=1'dx for DUT and TB

output:

image

DUT side [0]=d_tb_drive:x q_dut_sample:x
test side [3]=d_tb_drive:x q_dut_sample:x

Here at negative edge the DUT is triggered default input #1step and output #0 input #1step: denotes the negative time delay from the edge of the clock(negative edge). when all the input are ready and steady for the sample. the sampling the signal is done before the edge of clock. output #0 : At the negative edge (DUT) at #0 it drive the sampled value i.e output skew.

@5ns paint

DUT side [5]=d_tb_drive:0 q_dut_sample:0

2nd duty cycle @(posedge clk & negedge clk)

at the positive edge the test is triggered
wave form @posedge clock

image

test side[13]=d_tb_drive:0 q_dut_sample:0

Here at negative edge the DUT is triggered wave form @negedge clock

image

DUT side [15]=d_tb_drive:1 q_dut_sample:1

**3rd duty cycle @(posedge clk & negedge clk) **

at the positive edge the test is triggered
wave form @posedge clock

image

test side[23]=d_tb_drive:1 q_dut_sample:1

Here at negative edge the DUT is triggered wave form @negedge clock

image

DUT side [25]=d_tb_drive:1 q_dut_sample:1

output of d_ff for all clock cycles

image

Transcript output

dff_cb_ss1