AMBA Based Microcontroller

                     Fig: The Typical AMBA based Microcontroller

The microcontroller which is based on AMBA consists of a high-performance system bus (AMBA AHB or AXI ),which is able to sustain the external memory band-width, on which the CPU on-chip memory and other Direct Memory Access (DMA) devices reside. AMBA bus protocol basically used for data communication purpose between masters and slaves. This communication bus provides a high bandwidth interface between the elements that are involved in the most of the transfers. If the system contains devices of both high and low-performance nature, then for high performance AHB, AXI bus protocol is used and for low performance mostly APB is used. As both high and low performance is in the same system then bridge concept comes in the picture as shown in above figure.

Among the three AMBA protocols APB bus protocol structure requires less power and it is simplest one to design when we compare it with AHB bus protocol structure but having low performance as compared to AXI. Similarly, the AMBA AXI bus protocol consumes moderate power and will give us a better performance as com-pared with APB. Hence if we require high performance then AXI bus protocol structure is selected for the SOC designs. The AXI is Interconnect based bus, hence multiple master multiple slave simultaneously communication is possible, making it much more efficient.

AXI READ and WRITE Channels

              Fig: Read and write Channel

In AXI(Advance extensible Interface bus) as the Five channels

1. Write Address channel(AW)
2. Write data channel(W)
3. Write Response channel(B)
4. Read address channel(AR)
5. Read data channel(R)

WRITE OPERATION

               Fig: Write operation channels.

1. Initially the master initiate the transactions, primarily in the write Address channel(AW) we send the address from AXI-master to the AXI-slave and set some of the control signals such as AWLEN,AWSIZE,AWBURST etc.
2. In the next channel, write data channel(W) we send the data for that address from the AXI-master to AXI-slave.
   3.Finally from the Write Response channel(B), from the slave side, if data is successfully return in the slave address than we get the write response.
3. In the above figure we can observe that multiple write data is transferred from master to slave it depends on the burst operation.

READ OPERATION

                      Fig: Read operation channels

1.Firstly, the master-AXI send the address from which AXI-slave it want to read the data and set some of the control signal, it is done using the Read Address channel(AR).
2. Then finally, the AXI-slave send the data of the particular address to the AXI-master through Read data channel(R).

AXI INTERCONNECTION

                      Fig: AXI multiple master and multiple slave Interconnection

1. AXI Interconnect is responsible for connecting the AXI-master and AXI-Slave.
2. The AXI Interconnect act as the Slave device for AXI master and master device for the AXI slave.
3. Each slave hold the address which are connected to AXI interconnect. The AXI master is responsible for initiating the transaction whether Read or write to any of the slave depending on the address range of slaves.
4. Example in the above Figure each of the slave (i.e USB,UART,PIO) we have the starting address and ending address, whenever any of the AXI master (i.e CPU1,CPU2) want to initiate the read or write transaction to memory block i.e for slave2:UART master as to send the address within the range of slave3 and same rule follow for the other slaves in the AXI interconnection.
   5.In AXI interconnect, the every transaction come in to interconnect, the interconnect holds the decoder address table, it will first look the address of AXI transaction and route the transaction to the particular slave which holds that address.