Clock Fine Delay Control - DLS-Controls-Private-org/MBF-docs GitHub Wiki

Fine delay over DAC output clock and turn clock synchronisation. All PVs described here are prefixed with $(device).

DAC Delay

There is also a global control for DAC fine output delay which affects both axes simultaneously:

Title	PV	Description
Fine	:DLY:DAC:FINE_DELAY_S	This control adds an extra delay to the DAC output clock in units of 25ps. A delay of 0 to 23 units can be set. Note that this delay affects both channels. This delay is available for fine adjustment of the closed loop delay.
Coarse	:DLY:DAC:COARSE_DELAY_S	This control adds an extra delay to the DAC output clock in units of either 400ps or 330ps (depending on the PLL configuration). Due to programming limitations of the clock controller chip, this can only be increased, or reset to 0 by triggering :DLY:DAC:RESET_S. Any value in the range 0 to 7 can be set.
	:DLY:DAC:STEP_S	Processing this PV will add one to :DLY:DAC:COARSE_DELAY_S, so long as the value is not then out of range.
	:DLY:DAC:RESET_S	Processing this PV will reset the coarse delay to zero.
Total	:DLY:DAC:DELAY_PS	This computes the total extra delay in ps as configured above.
FIFO	:DLY:DAC:FIFO	This shows the status of the DAC FIFO, bridging the data flow from the ADC clock to the adjusted DAC clock. Normally half the FIFO is in use as shown, though towards the higher end of the coarse delay the FIFO usage can increase by one. If possible, keep the adjustments so that this FIFO reads as shown.

Turn Clock

These PVs are used to manage the synchronisation of the turn clock to the machine revolution clock. This system expects that the revolution clock is connected to the EXT TRIG input of the FMC-500 card.

Title	PV	Description
Sync	:DLY:TURN:SYNC_S	Processing this PV will cause the internal turn clock to be synchronised with the external clock trigger. This is a single event, and it is expected that the system will remain locked indefinitely after a single sync event after system startup.
Status	:DLY:TURN:STATUS	This indicates the status of the turn clock synchronisation: "Unsynced" at startup, "Armed" if still waiting for a turn clock event, "Synced" once seen. If the status shows Armed then it is likely that the turn clock is not connected.
Clock errors	:DLY:TURN:RATE	On each internal turn clock event we check whether the external turn clock is seen. This PV, updated at 5Hz, indicates how often the two clocks are not synchronous
Delay	:DLY:TURN:OFFSET_S	This programs a delay from the synchronised turn clock to the system turn clock used for all bunch alignment. Setting this will determine which bunch in the machine fill is treated as "bunch zero" by the feedback processor.
Skew	:DLY:TURN:DELAY_S	If the external turn clock is present but clock errors (:DLY:TRG:TURN:RATE > 0%) are seen then there may be metastability between the external trigger and the internal clock. This control adds an external delay (in units of 78ps) so that the metastable point can be avoided.

Note that a half-step delay in an earlier version was removed because of unavoidable glitches, see forum posting on TI forum.