FSM Notes

This wiki page is an attempt to write up some notes on the VATA FSM.

State Machine Diagrams

To build the state machine diagrams, you will need graphviz installed

Go to the /cores/vata_460p3/doc directory, and run make. This will build:

• Data acquisition and readout FSMs (data-acq-fsm.png)
• Hopefully more soon!

Comparison to IDEAS datasheet

Parsing of section 2.4: "Acquisition, Conversion and Read-out of the ADC", pg. 26, VATA460.3_DS-1R16

1. Initially, ASIC is in mode M3, "acquisition mode". While in M3, i4 must be high to keep ADC at reset values.
2. In M3, ASIC outputs trigger on o6. External system waits before settings hold on i1.
3. Once held, ASIC transitions to mode M4, "conversion".
4. Once the "ASIC has settled", i4 can go low, enabling the ADC
5. Between 100ns - 200ns after i4 goes low, first rising edge of the i1 clock. i1 clk period is 100ns according to Fig. 8.
6. During conversion, i3 should be high to enable "conversion done" flag output.
7. i1 clock continues until all channels are converted, and ASIC flags conversion complete on o5. OR, after 1024 clock cycles conversion is complete without flag on o5.
8. i1 goes low, and then the ASIC is switched to M5, "data readout mode".
9. Data clocked out on o6. Clock period is 650ns according to Fig. 8. After last bit, i4 goes high, and ASIC should be set back into mode M3.

Differences between data sheet and implementation?

• Point 4. Once "ASIC has settled"? Currently i4 is lowered 110ns after latching mode M4. Is this enough time? Fig. 8. shows 100ns.
• Point 6. OR after 1024 clock cycles. We are currently not handling this!!!