Notes on the AXI Calibration DAC IP

AXI registers

The peripheral is set up with 8x32-bit registers that are all used as write registers.

Register assignments:

• Register 0: Testing state.
  • reg0(0) = calibration pulse enable
  • reg0(1) = vata trigger enable
  • reg0(2) = vata fast-or trigger disable
• Register 1: Initiate pulses on rising edge of reg1(0)
• Register 2: Calibration pulse width
• Register 3: Vata trigger out delay
• Register 4: Number of pulses to generate. If 0, then send out pulses as long as reg1(0) is high
• Register 5: Delay between pulses
• Register 6: Cal Dac send trigger (on rising edge of reg6(0))
• Register 7: Cal Dac value

Previous allocation:

Write register

For initiating calibration pulses:

• register 0: set to 0x1 to initiate pulse sending. Needs to be set back to zero when done (this will need a fix once the ability to send multiple pulses has been implemented).
• register 1: set to the pulse width in AXI clock cycles.
• register 2: set the VATA trigger out delay. Can be no longer than the pulse width set by register 1.
• register 3: set to the number of pulses to generate. Note that this functionality is not yet implemented. Note to Sean: Maybe implement this in the AXI_s00 instantiation rather than the core hdl itself?

For controlling the calibration DAC:

• register 4: set to 0x1 to transmit SPI data to the DAC after setting the pulse height value. A rising edge is required to initiate transfer, so make sure you set it back to zero when done.
• register 5: First 12 bits (0xFFF) set the calibration DAC height.

Currently unused:

• register 6
• register 7

Read register

N/A