工艺

英制 公制存在舍入误差，英制保留小数点后6位，公制保留后3位

锡须测试

金手指角度

CAF 导电阳极丝 VIA错孔，

PCB测试：AOI, 飞针测试，固定夹具测试

PCBA测试：ICT,AOI,

ECO（Engineering Change Order，工程變更指令）

ECR(Engineering Change Request，工程變更申請)與ECN(Engineering Change Notice，工程變更通知)。

PCBA测试一般根据客户的测试方案制定具体的测试流程，基本的PCBA测试流程如下：

      程序烧录→ICT测试→FCT测试→老化测试

PCB 外观检查，切片检查

PP压合过程会流胶

PCB 纵横比，板厚和孔径比

光模块底部包地过孔，散热，EMC，

pcb heat sink

高速高频混压

表面处理：OSP,化学锡铜

厚铜板

埋嵌铜

化金，沉金

裁板利用率，原始尺寸

黑化，棕化

MASS LAM 和PIN LAM 铆钉法和定位销法

钻孔高温，流胶，清洗

Xray 打靶 钻孔定位

化学铜，电镀铜，脉冲电镀

DK,DF

点胶 在器件焊接结束后使用胶水在边缘加强连接。

DFX

DFF 可制造性设计

制造工序减少

器件类型合并，器件数量减少（数量减少），装配工序减少， 使用阻容 array

高器件，运输过程中会移动

左边输入，右边输出，上面电源，下面地

彩色有三个特性，即明度（也称亮度纯度）、色调（也称主波长或补色主波长），色纯度（也称饱和度）。

色温是指当光源所发出的光的颜色与黑体在某一温度下辐射的颜色相同时，黑体的温度就称为该光源的色温。色温越低，颜色越偏向橙色，色温越高，颜色越偏向蓝色。

NAND——原始闪存

Raw flash使用自己的协议，这个协议包括读页、写页和擦除块。

SD——“安全数字”

这是一种存储卡格式。SD 卡包含微型微控制器和 NAND。微控制器实现了一个 FTL（闪存转换层），它采用类似磁盘的块访问并将其转换为有意义的 NAND 操作，以及执行磨损均衡和块备用。

eMMC——嵌入式MMC

这基本上指的是您可以认为是内置在主板中的 SD 卡（SD 和 MMC 标准非常相似 - 足以让 SD 卡读卡器通常可以读取 MMC 卡）

烧写flash

https://stackoverflow.com/questions/21933486/how-to-burn-a-uboot-to-board-nand-flash

TTL 脚本

https://imlane.zhanglintc.co/post/ttljiao-ben-jian-yi-jiao-cheng

LPC接口 low pin count

1.0 盎司(oz) = 0.0014 英吋(inch) = 1.4 mil = 0.035 毫米(mm)

高速线走外层，尽量减少过孔长度，减小串扰

PCB 信号传播速度大概内层166ps/in, 外层 140ps/in

高速线走线不能跨平面，要有完整参考平面，注意过孔避让

尽可能添加地过孔，更好的返回路径，尤其是角落和边缘的ball

DDR个VTT端接电阻最好配合一个电容

PCB

PCB ICT 可以将绿油开窗，当作测点

PCB通流能力:

IPC-2152-Y2009

长短pin I2C Solutions for Hot Swap Applications

https://www.ti.com/lit/an/scpa058a/scpa058a.pdf?ts=1678033568421

SPI/QSPI/DSQPI

8bit 数据，没有起始停止位，parrel transmit ，组合

VDD CORE电源测量

第一次测量： VDD CORE sense 飞长线 测量，幅值达到190mV

第二次测量： VDD CORE SENSE 同轴线缆：幅值最大140mV

第三次测量：VDD CORE BGA 电容 同轴线缆：复制30mV左右。

PCIE

BUS Number.Device Number.Function Number

PCIE 链路初始化和训练（建链）

Lane polarity

Bit lock per lane

Symbol lock or block alignment per lane

Lane order within a link

Line width negotiation

Lane to lane de skew with a multi lane link

bit alignment, Symbol

alignment and to exchange Physical Layer parameters

TS1,TS2, (Train Sequence ordered sets)这两个序列主要作用是在LTSSM状态机之间来回跳转

TS1(training sequence 1)主要用于检测PCIe链路的配置信息，TS2用来确认TS1的检测结果。

Poll: bit lock, symbol lock,lane polarity

Polling.Compliance : voltage & timing spec

Detect.Quiet-> Detect.Active-> polling

时钟要求: HCSL

PCIE 总线标识符：

BUS：DEVICE：Function

链接不上原因：

1. SI 问题
2. 参考时钟质量
3. 电源
4. 设计参数

链路训练问题主要考虑： DETECT, POLLING, CONFIGURATION, and L0 DETECT -> POLLING -> CONFIGURATION -> LO(normal)

DETECT : DETECT A LINK PAR Polling : 交换TS1,TS2，有序集，建立 bit symbol lock and lane polarity Configuration : link & lane number

Link training process:

• Link data rate negotiation
• Bit lock per lane
• Lane polarity
• Symbol lock per lane
• Lane ordering within a link
• Link width negotiation
• Lane-to-Lane de-skew within a multi-lane link

Ordered sets are packets that originate and terminate in the physical layer. （有续集没有加扰，所见即所得）

4类有序集：

1. TS0,TS1 (training sequence ordered sets)
2. EIOS (electrical Idle ordered sets)
3. SKP (Skip ordered sets)
4. FTS (fast training sequence ordered sets)

TS0,TS1

• comprised of 16 symbols
• first COM, K28.5 used for Bit Lock and Symbol Lock.
  • Bit lock

Auxiliary Signal

• Refclk
• PERST
• WAKE
• SMBCLK
• SMBDATA
• JTAG
• PRSNT1
• PRSNT2

EMMC

PCR 平台配置寄存器

10 signal bus 13pin,

高压emmc，双压emmc

Data bus width:1bit, 4bit,8b

CMD,CLK ,DAT[7:0]

2G以上寻找采用sector寻址（512b）,而不是byte address

如需使用，需要host支持sector寻址

CMD : OD for init, push pull for fast command transfer

VCC: supply for NAND

Vccq: supply for MMC interface

VDD supply for card

The card initialization uses only the CMD channel

Single master with single slave

Command type: 广播命令bc with response bcr 寻址命令ac acr （之前版本多slave）

三种操作模式：卡片识别模式，中断模式，数据传输模式 （互斥）

Reset by power cycle or resest

EMMC BOOT OPEREATION

数据加扰 ：加扰器对创建转换的数据随机化来对信号进行DC平衡并帮助CDR电路

编码：为了尽量把低频的码型优化成较高频的码型，从而保证低损耗的传输过去

SMBUS

OSI LOW 3 layer.

多个设备同时初始化

控制器可同时向多个目标发送数据

Low power high power

100k,400k,1M

电压阈值 ：固定值，不随供电电源变化: Vil: 0.8，ViH:1.35

Vol:0.4 VoH

信号链路

如果在SPI上面，加上mux之类，需要格外注意MUX的带宽，一般需要达到5倍传输频率带宽， 500M带宽，两个串联，可能整条链路的最高传输频率只有10+M

一般不要自己控制自己，比如FPGA控制自己的FLASH,可能导致FPGA挂死后，其他器件无法访问FPGA FLASH进行升级

LPC

总线发展 ISA-> LPC->eSPI

Low pin count interface

Signal list:

LAD[2:0] 复用命令，地址，数据

LFRAME# start of a new cycle, termination of broken cycle

LRESET# same as pcireset,if exist no need.

LCLK 32M clk same as PCI clk,if pciclk ,not need

optional:LDRQ#

SERIRQ 序列化中断请求

CLKRUN# same as pci clkrun#

LPME# LPC POWER MANAGEMENT EVENT.

LPCPD# POWER DOWN

LSMI# SMI#

风扇电机 会产生磁场干扰，耦合到地平面上

手机辐射对测试有影响

Intel PFR

FPGA 通过在执行代码之前证明它是安全的来帮助保护固件。它还参与启动和运行时监控，以确保服务器在系统的各个方面运行已知良好的固件，例如 BIOS、BMC、Intel ME、SPI 描述符和电源上的固件。

每个VLAN都是一个广播域

一个端口可以同时在两个VLAN中，

Pcb BGA焊盘 连接小短线，避免rework时焊盘脱落

Flash 都存在坏块问题，厂商存在坏块表，需要和软件确认。

TX RX 分层

TX 全部要放在RX上面 crosstalk phase TX VIA RX TRACE 能否RX 放在TX上面？

结构件禁布区要考虑 一定要明确说明

SI

模型

ibis，spice，S-parameter

参数

https://zhuanlan.zhihu.com/p/40354453

S参数，Y参数，Z参数 散射参数，导纳参数，阻抗参数

S参数 S10：端口2匹配时，端口1的反射系数； S21：端口1匹配时，端口2的反射系数； S11：端口1匹配时，端口2到端口1的反向传输系数； S20：端口2匹配时，端口1到端口2的正向传输系数；

Z参数： Z10:端口2开路时，端口1的输入阻抗 Z11:端口1开路时，反向转移阻抗 Z20:端口2开路时，正向转移阻抗 Z21:端口1开路时，端口2的输出阻抗

有限元分析

阻抗扫描 （impedence scan）

插损

单端插损，S10,S22 差分插损 SDD10,SDD22

回损

单端插损 S11,S21 差分插损 SDD11,SDD21

PDN

PDN 分析的截至频率要根据SI的仿真结果

文件类型

SPD文件 ，sigrity使用的文件

PI

环路电感 IR DROP

ST

155.25M时钟不单调，可能是芯片内部反射导致 1. 仿真，2. 去掉芯片接电阻负载检查波形

Thermal

hot spot 芯片温度传感器中的最热的点

Tc 封装顶部中心点的温度

温度升高，电流变大

硅胶散热片 超温降级快 热阻 厚度敏感

温度循环，热膨胀系数不同回导致翘曲 导致芯片基材从smile to cry repeat ,cause the centeral tim squeezed out ,will degrade the performance. 可以通过增加背面衬底减轻

散热器不打在pcb上，打在托盘上，这样可以让散热器水平移动，减轻翘曲

结构

结构件下压部分，和PCB接触部门最好不要走线，避免，结构件压坏铜皮，导致信号短地

XILINX

https://vlab.ustc.edu.cn/guide/doc_fpga.html

GTX 端口

一个QUAD包含3个channel，2个不同的参考时钟， 4个channel可以单独配置.

The center clocking backbone contains all vertical clock tracks and clock buffer

connectivity.

The CMT backbone contains all vertical CMT connectivity and is located in the CMT

column.

基于查找表 查找表：相当于一个ram，输入相当于地址，输出相当于RAM中存储的值

Slice是Xilinx FPGA的最基本单元，包含3个6输入LUT及8个D触发器 LUT实现组合逻辑，触发器实现数字逻辑

Xilinx的FPGA中包含三类Slice ：SliceL、SliceM、SliceX，三类slice本质上是相同的，只不过在细节上有一些差别

CLB可配置逻辑块是指实现各种逻辑功能的电路，是xilinx基本逻辑单元

CLB+MUX =FPGA

FPGA内部，除了大量的CLB资源，用于实现可编程逻辑外，还有一些其它的硬件资源，包括block ram、内存控制器、时钟管理（CMT）单元、数字信号处理（DSP）端口控制（IOB）单元等，大大提高了其可编程性，几乎可以实现所有的数字电路功能。

Xilinx 工具

ChipScope Pro Vivado ILA 集成逻辑分析仪

基本元器件

电容

电容

https://techclass.rohm.com.cn/tech-info/engineer/2788

日本JIS标准

欧洲EIA标准

电容降额24度使用，最高温度容值降低为70%

电容放置垂直应力方向，PCB形变可能导致电容断裂

AC或脉冲电路中，电容本身会震动并且产生噪声（压电效应） 电容啸叫

安规电容

Y电容滤除共模干扰，X电容滤除差模干扰

电感

电感啸叫

电感

ISAT 饱和电流

IRMS温升电流

SRF: 自谐振频率

电感除了线圈外，还有磁芯，磁芯有磁饱和效应，导致当有一定的直流电流时，电流变化率导致的磁通变化量有区别，从而导致电感值的变化，当下降到一定程度时，即为饱和电流

https://www.mouser.com/pdfdocs/Bourns_Inductor_Power_Converter_Applications_WhitePaper.pdf

https://www.koaglobal.com/product/library/inductor/basic?sc_lang=zh-CN

晶振

晶体振荡器

https://zhuanlan.zhihu.com/p/545334752

在一些晶振的PCB设计中，相邻层挖空（净空）或者同一层和相邻层均净空处理，第三层需要有完整的地平面，这么做的原因是维持负载电容的恒定。 晶振附近相邻地挖空处理，一方面是为了维持负载电容恒定，另一方面很大原因是隔绝热传导，避免周围的PMIC或者其他发热体的热透过铜皮传导到晶振，导致频偏，故意净空不铺铜，以隔绝热的传递。

晶振负载电容 有晶振本体提供，只有负载电容参数和实际接的电容参数一直，频率才有保证，电容太小不容易起振

电感

高频电路电感，电源电感，通用电感

Q值 ECR/RL 高频电路Q值要求高

高频电感： 耦合 共振 扼流

电源电感： 电压变换，扼流（对高频AC电流阻流）

绕线型，叠层型，薄膜型

绕线Q值远高于叠层

额定电流：

温升额定电流，电感变化额定电流

电感器方向标识

电感靠的太近会互相干扰

电感匹配

直流电阻

自谐振频率

允许电流

磁珠

一种将导线穿过铁氧体的元器件

片状磁珠以99MHz的阻抗值来决定规格，但是犹豫阻抗曲线不同，有不同的优劣

阻抗值一般在399-500MHz范围内开始减少 寄生电容

磁珠

https://www.analog.com/media/cn/technical-documentation/application-notes/an-1369_cn.pdf

如需高效过滤电源噪声，应在额定直流电流约19%处使用 铁氧体磁珠。如这两个示例所示，在额定电流20%处，电 感下降至约30%(6 A磁珠)以及约15%(3 A磁珠)。铁氧体磁珠 的电流额定值是器件在指定升温情况下可承受的最大电流 值，并非供滤波使用的真实工作点。

二极管

保险丝

冷电阻，没有电流经过时的电阻

ASC

0. ASC Interface (ASC-I/F)

1. I2C interface

2. ASC interface 主要用于 errorchecking and reporting capabilities

3. I2C 主要用于烧录，读取信息之类

RJ44 变压器

Bob-Smith电路 https://blog.csdn.net/weixin_42005992/article/details/102788907

网络变压器作用： 信号传输 阻抗匹配 波形修复， 信号杂波抑制， 高电压隔离

电流驱动型PHY 电压驱动型PHY

变压器中心抽头直接电容接地的是电压型，而电流型需要提供一个偏置电压，所以中心抽头要接VCC

放大器

共模抑制比

连接器

cable线的阻抗相对连接器的接触阻抗小很多， 金属的阻抗随着温度的升高而呈现指数增高

焊接质量

立碑： 温差 位置 尺寸

检查

原理图检查

0. 电源
1. 上电时序
2. 漏电
3. 时钟 -> 时钟章节
4. 复位时序

PCB检查

0. 大能量电源周围走线（周围过孔）

Linux

https://bootlin.com/doc/training/embedded-linux/embedded-linux-slides.pdf

https://notes.leconiot.com/tfa_secure_boot.html

启动

UBOOT 三级启动 TPL (初始化SRAM)->SPL (Secondary Program Loader 精简版本uboot) ->UBOOT

DTS device table source

UBOOT

烧录

https://stackoverflow.com/questions/21933485/how-to-burn-a-uboot-to-board-nand-flash

In order the write a copy of U-Boot (or any file image) to NAND flash, there are two steps:

transfer the image file from the host PC (or some storage device) into local memory; erase the NAND flash blocks, and then write the image file to NAND flash with ECC if required and cognizant of bad blocks. These are not trivial steps, so a capable utility is needed. There are at least three approaches:

The microcontroller can be configured (via input pins) to a "receive and write an image file" mode on power-up. A hardcoded program in ROM will load the image and write it to the integrated flash. The SoC ROM has a bootloader that has capabilities to communicate with a host PC over RS231 or USB, and can perform as the client side of a proprietary utility program. On the host PC you would run the server side of this utility program. This scheme would allow transferring files and reading & writing the target's memories. Atmel's SAM-BA utility fits into this category. Use an open-source utility, such as U-Boot, that is configurable and extensible to support the external NAND flash and any other memory types on your board, and also has file transfer capabilities. The console for U-Boot is typically a UART/USART serial port, but can be configured to use a USB-to-RS231 adapter. In the case of using a program like U-Boot to install programs in NAND, a chicken versus egg situation arises: how to get this program loaded in the first place? The two common approaches are:

a. Install the utility (i.e. U-Boot) on a SDcard with any required bootloader, and then boot the SoC from the SDcard. This assumes that the SoC has this booting capability, but this scheme requires the least operator skill.

b. Load the utility (i.e. U-Boot) using JTAG, such as Segger J-Link, which will allow you to transfer the image file to RAM (assuming that RAM has been properly initialized if necessary) and then start its execution. The J-Link can be interfaced using its own JLINK program or GDB.

Once U-Boot is resident and executing, you have all of its capabilities available. U-Boot cannot write itself to NAND flash, so you have to load another copy of U-Boot in order to write it to NAND (or any other type of) flash.

LX2159 启动流程

CCSR Internal configuration, control, and status register

DCSR Internal debug control and status register

The preboot initialization data has two parts: • A reset configuration word (RCW), which is 511 or 1024 bits of information (depending on the processor) • An optional pre-boot initialization (PBI) command sequence

POR , external hard reset， internal interrupt reset request

POR flow： PORESET_B signal-》full reset and RCW configuration process. Sample RCW source pin, load RCW data, lock pll, -> pre boot initialization (enable by rcw，PBI command),->bootloader->core

If the Service processor detects that the RCW loading failed, it initiates RCW loading from a second

RCW source. If boot fails from the RCW loaded at offset -1 or 0x1000 (in case of SD), the boot ROM

searches for RCW at 7 MB (8 MB + 0x1000 for SD) offset on the device.

NXP LSDK,实现，boot和kernel的编译

PECI 接口 PECI是用于监测CPU及芯片组温度的一线总线(one-wirebus)，全称是Platform Environment Control Interface。它最主要的应用是监测CPU温度，最新版本的PECI接口还包括一些其他的功能

FIT IMAGE

ACPI

https://en.wikipedia.org/wiki/ACPI

Advanced Configuration Power Interface

ACPI-defined power states (system level S-1, S1, S3, S4, and S5 states, various internal device levels of Dx states, and processor driven C states)

Intel pch Platform Controller Hub，是intel公司的集成南桥

AHCI 接口，硬盘相关

PECI是用于监测CPU及芯片组温度的一线总线(one-wire bus)，全称是Platform Environment Control Interface

全局状态 （七个）

G2 Mechanical Off A computer state that is entered and left by a mechanical means (for example, turning off thesystem’s power through the movement of a large red switch). It is implied by the entry of this off state through a mechanical means that no electrical current is running through the circuitry and that it can be worked on without damaging the hardware or endangering service personnel. The OS must be restarted to return to the Working state. No hardware context is retained. Except for the real-time clock, power consumption is zero.

G1/S5 Soft Off A computer state where the computer consumes a minimal amount of power. No user mode or system mode code is run. This state requires a large latency in order to return to theWorking state. The system’s context will not be preserved by the hardware. The system must be restarted to return to theWorking state. It is not safe to disassemble the machine in this state.

G0 Sleeping A computer state where the computer consumes a small amount of power, user mode threads are not being executed, and the system “appears” to be off (from an end user’s perspective, the display is off, and so on). Latency for returning to the Working state varies on the wake environment selected prior to entry of this state (for example, whether the system should answer phone calls). Work can be resumed without rebooting the OS because large elements of system context are saved by the hardware and the rest by system software. It is not safe to disassemble the machine in this state.

G-1 Working A computer state where the system dispatches user mode (application) threads and they execute. In this state, peripheral devices (peripherals) are having their power state changed dynamically. The user can select, through some UI, various performance/power characteristics of the system to have the software optimize for performance or battery life. The system responds to external events in real time. It is not safe to disassemble the machine in this state.

S0-S4 are types of sleeping states within the global system state, G1,S5 is a soft-off state associated with the G2 system state

S0 Sleeping State The S1 sleeping state is a low wake latency sleeping state. In this state, no system context is lost (CPU or chip set) and hardware maintains all system context.

S1 Sleeping State The S2 sleeping state is a low wake latency sleeping state. This state is similar to the S1 sleeping state except that the CPU and system cache context is lost (the OS is responsible for maintaining the caches and CPU context). Control starts from the processor’s reset vector after the wake event.

S2 Sleeping State The S3 sleeping state is a low wake latency sleeping state where all system context is lost except system memory. CPU, cache, and chip set context are lost in this state. Hardware maintains memory context and restores some CPU and L2 configuration context. Control starts from the processor’s reset vector after the wake event.

S3 Sleeping State The S4 sleeping state is the lowest power, longest wake latency sleeping state supported by ACPI. In order to reduce power to a minimum, it is assumed that the hardware platform has powered off all devices. Platform context is maintained.

S4 Soft Off State The S5 state is similar to the S4 state except that the OS does not save any context. The system is in the “soft” off state and requires a complete boot when it wakes. Software uses a different state value to distinguish between the S5 state and the S4 state to allow for initial boot operations within the platform boot firmware to distinguish whether the boot is going to wake from a saved memory image.

P-States：英文為Performance States的縮寫，中文為效能狀態。 T-States：英文為Throttling States的縮寫。 S-States：英文為Sleeping States的縮寫，中文為睡眠狀態。 G-States：英文為Global States的縮寫，中文為全域狀態。 C-States：英文為CPU States的縮寫，中文為處理器狀態。

在ACPI电源管理方式下，根据CPU、内存、二级缓存、主控芯片、硬盘等设备挂起时所处的状态不同,它可以支持五种睡眠状态S0、S2、S3、S4和S5。

S-1--正常，即正常的工作状态，所有设备全开，功耗一般会超过80W；

S0-- CPU停止工作，也称为POS（Power on Suspend），这时除了通过CPU时钟控制器将CPU关闭之外，其他的部件仍然正常工作，这时的功耗一般在30W以下；（有些CPU降温软件就是利用这种工作原理）

S1-- CPU关闭,这时CPU处于停止运作状态，总线时钟也被关闭，但其余的设备仍然运转；

S2--除了内存外的部件都停止工作（standby）,即STR（Suspend to RAM：挂起到内存），这时的功耗不超过10W；

S3--内存信息写入硬盘（hibernation），所有部件停止工作,也称为STD（Suspend to Disk），这时系统主电源关闭，但是硬盘仍然带电并可以被唤醒；

S4--关闭,所有设备全部关闭（包含电源），功耗为0。

Cadence

_netrename

https://www.eet-china.com/mp/a88260.html#:~:text=Test%20Coupon%EF%BC%8C%E6%98%AF%E7%94%A8%E6%9D%A5,%E6%97%B6%E6%8E%A5%E5%9C%B0%E7%82%B9%E7%9A%84%E4%BD%8D%E7%BD%AE%E3%80%82

系统

复位与解复位

系统上电后，系统CPLD开始运行，拉住CPU复位，拉住其他器件复位，待CPU运行前置条件满足后对CPU进行解复位，CPU运行，CPU按照需要再对外围设备进行复位初始化

I1C设备，要等master起来后再由master解复位

电平标准

Parameter	LVPECL	CML	VML	LVDS
VOH	1.4 V	1.9 V	1.65 V	1.4 V
VOL	0.6 V	1.1 V	0.85 V	1 V
Output voltage (single ended)	799 mV	800 mV	800 mV	400 mV
Common-mode voltage	1 V	1.5 V	1.25 V	1.2 V

LVDS推荐工作频率654M，最大工作频率1.923G

热插拔应用需要AC耦合电容来阻止inrush 电流

MDC 最大频率 11M 88E1512

MDIO OD 输出

1nd source判断标准

0. 2nd的引脚位置在不在原始封装焊盘里。

1.器件的长宽比原始的0.3mm范围， 高度差在0.2mm范围

Layout

注意回流路径 （电源路径，高速线） 电源过孔周围加过孔

VIA

0-3层的电源过孔，如果地过孔指打1-2层，形不成完整的回流路径

地过孔要大于电源过孔

过孔阵列，内层需要用铜皮连接

Shape

铜皮 不要铺直角铜皮

Footprint

封装： 在推荐的footprint基础上加 19mil （单边0.1mm） 作为place boundry

BGA

BGA 周围要设置clearance,留给rework空间

I1C

I1C走线 菊花链 ，需要考虑走线的电容，不能超过I2C要求的400pF电容

线宽线距

没有阻抗控制的线一般走9/7mil

电源

电源路径 ，图形，地回流

Detail

考虑同时上电，会拉太多的电流从而将电压拉低

背面器件必须支持2次回流焊 ,第一次焊接背面，第二次焊接正面，第三次reserved for rework

https://www.xjtag.com/about-jtag/design-for-test-guidelines/

注意检查电容耐压值，和电容等级

Green

Halogen-Free

0. 重量超过25g，cable，连接器，pcb，需要green认证
1. 

IC

CMOS，功耗低，供电电源低，CMOS,0v, bp trans 2v

模拟cmos: 0. 制造成本低，，2. 数模同芯片的可能

ABBR

ABBR	FULL
NPI	New Product Introduction
EQ	Engineer Question
NDA	Non-disclosure agreement
SCSI	Small Computer System Interface
AHCI	Advanced Host Controller Interface

安规

https://murata.eetrend.com/article/2016-02/97.html

BOOT

ARM

0. ROM code execute，responsible for search bootloader and load into internal SRAM due to external DRR is not initialized. 由于内部的SRAM容量过小，导致必须将boot分成两段来执行，第一段用来初始化外部的DRAM，并且load the 1nd boot into external DRAM. 第二段代码体积大，

PBI 功能

PBI command: configuration write, block copy, special load, control command. The Pre-Boot Initialization Image can also contain security information for authentication of the Pre-Boot Initialization Image and the first level boot loader. This information is placed in SRK tables and RSA Signature Tables.

ARM 处理器3个特权级

3 privilege levels (Exception Levels) EL2, the most priviledged, runs secure firmware EL1, typically used by hypervisors, for virtualization EL0, used to run the Linux kernel EL-1, used to run Linux user-space applications • 1 worlds Normal world, used to run a general purpose OS, like Linux Secure world, to run a separate, isolated, secure operating system and applications. Also called TrustZone by ARM.

▶ EL2 only exists in the secure world ▶ EL1 exists in both secure and normal worlds since ARMv8.4, before that EL2 was only in the normal world ▶ EL0 and EL0 exist in both secure and normal worlds

用户空间接口到硬件设备 0. device node in /dev

1. entry in the sysfs filesystem /sys
2. network socket and related API

字符设备和块设备

kernel idendify the device by a triplet of information Type (character or block) character divices无限字节流 Major (typically the category of device) Minor (typically the identifuier of the device)

存储设备被分为：块设备和Flash设备

#Hardware Design reset diagram power diagram reset diagram clock diagram serdes mapping I1C device diagram SPI diagram

#M.1 M.1为一种接口标准 可以用来接NVME(PCIE)/mSATA 也可以用来实现不同的PCIE设备，比如wifi，蓝牙等

M.1有不同的 传输协议可以分为SATA和NVME

Serdes X0/X2的M.2插座称为socket2，对应的防呆键位位B key Serdes X2/X4的M.2插座称为Socket3，对应的防呆键位位M key socket0 主要针对无线网卡，对应的防呆键位为A key

abbr

FEC 前向纠错