• Upstream: port that points in the direction of the root complex
• Downstream: port that points away from the root complex.

Transaction Layer Packets (TLPs) (Top level message)

• exchanges Flow Control information
• supporting both software and hardware-initiated power management.

Three pcie address space : MEMORY I/O,configuration, Message

Link management and data integrity, include error detection & error correction.

reliably exchanging information

logic and electrical block

interface operation and logic information include interface initialization and maintenance

Logic

For backward compatibility,the link is 2.5GT/S with 8b/10b encode, and change to 8G/S with 128b/130b

8GT/S DATA STRUCTURE

2bits sync header + ordered set + data block（ frame token +TLP + DLLP）

32GT/S or higher , precode

PCIE link equalization to neogiate with transmit speed

Link initialize and train

Ordered sets are packets that originate and terminate in the physical layer. （有续集没有加扰，所见即所得）

Training sequences bit alignment, Symbol alignment and to exchange Physical Layer parameters

TS1,TS2 (Train Sequence ordered sets)这两个序列主要作用是在LTSSM状态机之间来回跳转,TS1(training sequence 1)主要用于检测PCIe链路的配置信息，TS2用来确认TS1的检测结果。
^⚓ EIOS: Electrical Idle Ordered Set

TS1: symbol 6 is D10.2, TS2: symbol 6 is D5.2 or EQ TS1/TS2

Link training 过程中的特殊序列字符编码 表征不同的功能

在 link training 完整对Link width, data rate，Lane reversal,polarity 的配置。

Link training process:

• Link data rate negotiation
• Bit lock per lane
• Lane polarity
• Symbol lock per lane
• Lane ordering within a link
• Link width negotiation
• Lane-to-Lane de-skew within a multi-lane link

• Complete LTSSM process

Poll: bit lock, symbol lock,lane polarity

Polling.Compliance : voltage & timing spec

Detect.Quiet-> Detect.Active-> polling

State	Description
Detect
Polling
Configuration
L0	Normal operational state
L0s
L1
L2
Recovery
Loopback
Hot reset
Disabled

low-power states: (L0s, L1, L2)

在配置阶段，使用的速率为2.5GT/s, GEN1

Detect.Quiet -> Electrical.Idle broken for 12ms -> Detect.Active -> Receiver detected -> Polling.Active

EIOS Detect Presence of Receiver by checking the impedance of Zrx_dc

• Receiver Detection： Check the impedance of Zrx_dc(40-60 ohm), Rx detection only occurred in 2.5GT/s, that's why DC RX impedance at GEN1 is specified. Receiver is detected based on the rate that the lines change to the new voltage.

???? How to exit Electrical.idle (check periodcally?) phy_rxelecidle exit

LTSSM will cycle between Detect.dile and Detect.active with a period of 12ms if NO link.

Polling.Active -> TS1/2 set -> - > Link control reg.enter complicane bot set 1-> Polling.Complicane TX 发送TS1 ordered set

Polling 中PAD是个字符，不是焊盘

configuration.idle: confirm scrambling

Pcie_recovery.drawio

一开始linkup 的速度是2.5GT/s, 如果双方支持更高的速率，可以通过recovery重新协商到更高的速率

Recovery.RcvrLock -> Recovery.RcvrCfg ->

send TS2 with speed change bit

Recovery.Speed -> Recovery.RcvrLock -> Recovery.Equalization ->

8G speed (after negeotiate to higher speed) Recovery.RcvrLock -> Recovery.RcvrCfg -> Recovery.Idle

Recovery.Idle similar to configuration.idle but at higher speed.

PCIE正常工作前，先要初始化建链，主要协商确定位宽已经频率，No firmware or operating system software is involved.

链路训练问题主要考虑： DETECT -> POLLING -> CONFIGURATION -> L0(normal)

• DETECT : DETECT A LINK PRESENT
• Polling : 交换TS1,TS2，有序集，建立 bit symbol lock and lane polarity
• Configuration : link & lane number

时钟要求: HCSL

LFSR
CRC
8B_10B
TLP: Transaction Layer Packets

• TX_P/N
• RX_P/N
• REFCLK_P/N

• Refclk
• PERST
• WAKE
• SMBCLK
• SMBDATA
• JTAG
• PRSNT1
• PRSNT2

• 同源时钟(CC)
• 非同源时钟(IR)
• 数据时钟（只有RC有参考时钟，endpoint时钟由serdes 通过CDR 恢复出来）

时钟到达device后，会经过两次滤波，一次是PLL滤波，一次是 CDR滤波

时钟要求: HCSL

• PCIE 电容放置要求： 过连接器，发送侧尽可能靠近连接器 不过连接器，尽可能靠近接受侧

PCIe 扩频 减小EMI

pcie支持向下扩频，调制范围为-0.5%-0%

链接不上原因：

1. SI 问题
2. 参考时钟质量
3. 电源
4. 设计参数

• 电源
• 时钟
• 复位
• 时序
• LTSSM
• 抓信号 TS

BUS Number.Device Number.Function Number

1. PCIe-Clock-Source-Selection.pdf
2. pcie-deep-dive-part-4-ltssm.html