DDR拓扑，空间富裕，走T型网络，空间紧张，走flyby 一般T型网络在频率超过1GHz ，信号质量会出现大幅度下降 flyby控制stub长度，时钟信号100mil，地址控制信号150mil，

DDR3使用flyby拓扑的前提条件：

SPD

SPD (Serial Presene Detct),存储内存条的配置信息 Understanding DDR4 Serial Presence Detect (SPD) Table

Bank Rank Bank Group Rank （Single-Rank, Dual-Rank or Quad-Rank） 一个内存模块可以包括多个rank, Rank其实就是一组内存颗粒位宽的集合。具体说，当颗粒位宽×颗粒数=64bits时，这个模组就是有一个RANK, 不同rank的访问通过DDR的CS信号来决定

3DS 3-dimensional stack

DDP : Dual-Die Package，比如两个

DDR X4,X8,X16 X32

X4,X8,X16,X32是根据DQ的数据宽度来定义的,比如X4 chip only has DQ[3:0]

• ODT1, CKE1, CS1_n and ZQ1 are for packages containing two x32 die stacked. These pins are NC for all other configurations.

Signal	Direction	Function
CK_t/c	Input	Differential input clock, Double edge sampling
CKE,(CKE1)	Input	Clock Enable,Negative activate Precharge, Self-Refresh or Power-Down mode; During Self-Refresh, Input buffer and CKE are disabled.
CS_n,(CS1_n)	Input	Chip Select, provides for external Rank selection on system with multiple ranks
C0,C1,C2	Input	Chip ID
ODT,(ODT1)	Input	On Die termination
ACT_n	Input	Activation Command Input, when activated, RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14
DM_n/DBI_n/TDQS_t, (DMU_n/DBIU_n), (DML_n/DBIL_n)	IO	Input Data Mask and Data Bus Inversion
BG0-BG1	I	Bank Group, Activate which Bank Group X4/8 have BG0,1,X16 only have BG0, Also determine which Mode Reg to be acessed
BA0-BA1	I	Bank Address, Activate which bank,Also determine which Mode Reg to be acessed
A0-A17	I	Address, Address provide OP-code during Mode Register Set commands. A17 only defined for X4
A10/AP	I	Auto Precharege,After read/write operation, Sample thish bit to dertermie whether auto-precharge is needed. High auto-precharge, Low No Auto-precharge
A12/BC_n	I	Burst Chop?, Sampled druing READ/WRITE to determine burst chop will be peformed. High, no burst chop,Low, burst chop
Reset	I	Reset
DQ	I/O	Data input/output
DQS_t, DQS_c,DQSU_t, DQSU_c,DQSL_t, DQSL_c	I/O	Data Strobe,Used for clock in Read & Write
TDQS_t, TDQS_c	O	Termination Data Strobe; Termination resistor function Only for x8. Must disabled in X4,X16, configured by Mode Register
PAR	I	Command and Address even Parity
ALERT_n	I/O	CRC or parity error output
TEN	I	Connectivity Test Mode Enable.
VDDQ	PWR	DQ power supply, 1.2 +/- 0.06V
VSSQ	GNG	DQ Ground
VDD	PWR	Power Supply: 1.2 V +/- 0.06 V
VSS	GND	Ground
VPP	PWR	DRAM Activating Power Supply: 2.5V(2.375-2.75V)
VREFCA	PWR	Reference voltage for CA
ZQ	PWR	Reference Pin for ZQ calibration

DM_n: Input Mask Sianal for write data, during write access, If DM_n activated, Input data invalid. DM_n dual edge sampling by DQS....more detail...

DBI_n: IO signal. If DBI_n activated(low), Data need to be inverted. IF disactivated, Data don't need to be inverted. DQS DQS 用作数据传输过程中的clock信号，Read:edge aligned. Write: centered in write data.For X16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7

• Page size = data width * Column Address Page size 表示当行地址确定后，被激活的地址空间。

DRAM size calculation: BG*BA*ROW*COLUMN*WIDTH

多个DDR颗粒的级联： 数据位串行排序，比如[chip0.DQ0,chip0.DQ1,chip0.DQ2,chip0.DQ3,chip1.DQ0,chip1.DQ1,chip1.DQ2,chip1.DQ3....] 地址位如何级联，地址不需要级联，和其他存储芯片通过CS来级联不一样，DDR只要地址选中，所有DDR会同事输出DQ，一个rank内组合成64个bit，同时访问.

• On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and DM_n/DBI_n/TDQS_t, NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. For x16 configuration ODT is applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM.

延迟锁定环 (DLL) 和锁相环 (PLL)

• DLL 可以自动调节信号的延迟，使两路信号相位一致（边沿对齐）

DM功能在写操作中的作用：当给定的字节lane的DM_n采集到低电平时，DRAM会掩掉DQ作为输入pin接收到的写操作数据。当给定字节lane的DM_n采集到高电平时，DRAM不会掩掉DQ作为输入pin接收到的写操作数据，而会写到其core中。

DBI功能在写操作中的作用：当给定的字节lane的DBI_n采集到低电平时，DRAM会反转DQ作为输入pin接收到的写操作数据。当给定的字节lane的DBI_n采集到高电平时，DRAM不会反转DQ作为输入pin接收到的写操作数据。

DBI功能在读操作中的作用：当写给给定字节lane的数据中‘0’的比特数大于4时，DRAM将会反转其输出到DQ作为输出pin上的读操作数据，并且驱动DBI_n pin为低电平。否则，DRAM将不会反转读操作数据，并且驱动DBI_n PIN为高电平。

TDQS功能：当TDQS功能被使能（enabled）时，DM & DBI功能就都不支持了。当TDQS功能被失能（disabled）时，DM和DBI功能将会按照下表27的描述方式被支持。当TDQS功能被使能（enabled）时，与TDQS_t/TDQS_c pins相同的端接电阻功能将被应用到TDQS_t/TDQS_c pins上。

[BG=Bank Group Address, BA=Bank Address, RA=Row Address, CA=Column Address, BC_n=Burst Chop, X=Don’t Care, V=Valid].

https://www.eet-china.com/mp/a64457.html

自刷新模式才可以修改时钟

Command Address Latency (CAL Mode), Command Address Parity (CA Parity Mode)

Command Address Parity Latency (PL)

Refresh cycle time (tRFC)

average Refresh interval (tREFI)

Write level 调节CLK & DQS之间的信号

!Pasted image 20230917173559.png

!Pasted image 20230917173719.png

Usercode -> DDR controller-> DDR PHY -> DDR

CL-tRCD-tRP-tRAS

• CL：内存的CAS延迟时间 CAS Latency (Column Address Strobe or Signal) (SPD byte 19)
• tRCD：内存行地址传输到列地址的延迟时间 ACT to internal read or write delay time
• tRP：内存行地址选通脉冲预充电时间 PRE command period
• tRAS：内存行地址选通延迟 ACT to PRE command period

1T timing 表示每个命令占用1个周期 2T timing 表示每个命令至少占用2个周期

DDR拓扑，空间富裕，走T型网络，空间紧张，走flyby 一般T型网络在频率超过1GHz ，信号质量会出现大幅度下降 flyby控制stub长度，时钟信号100mil，地址控制信号150mil，

DDR3使用flyby拓扑的前提条件：

DDR个VTT端接电阻最好配合一个电容

1. DDR4 Tutorial - Understanding the Basics