Type

object

Default

By default, the simulation stops after the specified number of clock cycles has been completed.

Description

Specifies the conditions for terminating the simulation. PROLEAD can stop the simulation when a set of primary output signals reach a defined state, such as when a "done" signal is set to logic 1.

Impact

None; select the option that best suits your design.

Examples

"simulation": {
    "end_condition": 
     [
         {
             "name": "done",
             "value": "1'b1"
         }
     ]
}

In this example, PROLEAD ends the simulation if a signal named done is set to one.