Welcome to the beginner's guide to PROLEAD for hardware design evaluation! Whether you're a hardware enthusiast, an engineer, or a designer, PROLEAD is here to assist you in evaluating your own masked hardware designs. With its powerful features and user-friendly interface, PROLEAD aims to simplify the evaluation process and help you maximize the potential of your designs. In this comprehensive guide, we will take you through the essential steps to effectively evaluate your hardware designs using PROLEAD. By the end of this guide, you will have a solid understanding of how to leverage this amazing tool and make the most out of its features.

Installation

Before diving into the evaluation process with PROLEAD, it's important to ensure that you have successfully installed the tool. If you haven't done so already, please refer to Installation for detailed instructions on the installation steps. Once you have PROLEAD up and running, we can begin exploring the step-by-step process of evaluating your masked hardware designs.

Implementation

The first step in evaluating the side-channel security of a masked hardware design is to design the masked hardware circuit itself. You have the flexibility to use any hardware description language of your choice. However, it is essential to ensure that your final design is synthesizable. To help you understand the concept of a masked hardware circuit and provide you with an example to work with, we have provided a masked VHDL implementation of the PRESENT S-box refered to as TI, PRESENT S-box, Uniform. In the following, we focus on this example. For more examples, we refer to our Examples.

Hint: Designing a masked hardware circuit can be a challenging task. However, there is a solution that can simplify the process and ensure provable security. If you are not familiar with hardware masking or want to streamline the construction of masked hardware designs, AGEMA can help you. With AGEMA, all you need to do is provide your hardware design without masking, and the tool takes care of the rest.

Synthesis

As PROLEAD expects a gate-level netlist written in Verilog, the next step in the process is to synthesize the RTL (Register Transfer Level) code of your design. Synthesis is the process of transforming the RTL description into an optimized gate-level representation suitable for evaluation. For a more detailed description of this step, we refer to Synthesis. To accomplish synthesis effectively, we recommend utilizing either the commercial Synopsys Design Compiler, or the open-source tool, Yosys. In the case of Yosys, we have already provided a ready-to-use synthesis script along with a custom cell library. If you opt for Yosys, you can execute the synthesis script on the RTL code of TI, PRESENT S-box, Uniform by simply typing the following commands:

cd yosys/syn 
bash synthesize.sh vhdl ../../examples/Hardware/PRESENT_Sbox_TI_d1_Uniform/rtl/ sharedSbox

Hence, we continue with the netlist created in this step.

Evaluation

In the final step, we utilize PROLEAD to assess the probing security of the generated netlist. Prior to running the evaluation, it is necessary for the user to provide specific details about the implemented design and the desired security parameter for analysis. Once the configuration is set, PROLEAD takes in the provided information along with the netlist to evaluate the design's security.

Customization

In addition to the netlist, PROLEAD requires an accompanying configuration file to customize its capabilities. PROLEAD offers a comprehensive set of specific settings, but there's no need to worry as many entries are only relevant in specific use cases, and the default values are generally sufficient. However, we provide a brief guide on how to configure the most crucial settings in PROLEAD. It is imperative that the user adjust the following settings without exception to answer the following questions:

Question	Setting
What's the name of the clock signal?	clock_signal_name
How many cycles the design runs?	max_clock_cycle
How is the design initialized?	no_of_initial_clock_cycles, no_of_initial_inputs
What inputs to simulate?	no_of_groups

All other settings are mandatory and initialized with default values and you can customize them in case you need them. Every available setting is documented under Settings. A minimal configuration file can look like this:

no_of_groups % number of groups to conduct the test, e.g., fixed vs. fixed, fixed vs. random, etc.
2

4'h$
4'h0

clock_signal_name    % name of the clock signal
clk

max_clock_cycle   % maximum number of clock cycles per run before checking the end_condition
5

no_of_initial_inputs   % number of primary inputs during the initialization
4

no_of_initial_clock_cycles   % number of clock cycles to initiate the run (start of encryption)
1

[3:0] sboxIn1 group_in0[3:0]
[3:0] sboxIn2 group_in1[3:0]
[3:0] sboxIn3 group_in2[3:0]
en 1'b1

Run

Finally, the design and PROLEAD are ready for evaluation. To simplify the process, we have provided an execution script for TI, PRESENT S-box, Uniform. You can simply execute the script by running ./run.sh. This script executes PROLEAD and redirects the console output to a separate file. To run PROLEAD manually, navigate to the main directory and execute ./release/PROLEAD. PROLEAD will evaluate a design by using the default command line parameters. You can find a list of all command line parameters in the Usage section. Specifically, you need to specify the path to the design file, the library file, and the config file as command line parameters.