Register Bank

The following sections present the main concepts about registers and a description of the implementation of the project's register bank.

Introduction

Registers are sequential circuits composed of Flip-Flops, and within the context of computer organization, they occupy the memory hierarchy's highest level.

One of its main characteristics is volatility, so the stored data is lost when its energy supply is interrupted. Therefore, its core function is simple: store a word of "N" bits for a certain period.

General overview

The registers commonly have the following terminals:

Size (bits)	Input/Output	Terminal name
N	Input	Data input
N	Output	Data output
1	Input	Clock
1	Input	Set/Reset
1	Input	Clock Enable

Table 01 - General register terminal description.

In an architecture, registers exist into two distinct classes: data registers, used by ISA (Instruction Set Architecture) and visible to the programmer, and auxiliary registers, primal for the correct functioning of the architecture but invisible to the programmer.

The register bank consists of a collection of data registers grouped together forming a bank that can be accessed through a defined terminal interface.

The next section describes this interface and provides implementation details.

RV16Cm's register bank specification

The adopted approach consists of a bank composed of 16 registers with words of 16 bits each. The table and the section below detail the adopted interface for the bank:

Size (bits)	Input/Output	Terminal name	Terminal Description
16	Input	WD3	Data Input
16	Output	RD1	Data Output 1
16	Output	RD2	Data Output 2
4	Input	A1	Data Output Selector 1
4	Input	A2	Data Output Selector 2
4	Input	A3	Data Input Selector
1	Input	CLK	Clock
1	Input	WE3	Write Enable

Table 02 - RV16Cm's register bank terminal description.

Each of the data buses (RD1, RD2, and WD3) is related to a corresponding selector (A1, A2, A3) that works with a decoder to "select" the corresponding register and make it available for reading (A1 and A2) or write operations (A3).

To perform a write operation to a specific register, you select it using the selector (A3) and then encode the desired data on the WD3 bus. Then, you enable the terminal WE3 and wait for the next clock transition. To finish the operation, disable the WE3 terminal.

Furthermore, the RD1 and RD2 buses work separately and asynchronously, and the zeroth register is always zero, following the RISC-V specification.

Code organization and implementation

The Register Bank's top module is located in the register_bank.v file and its interface is shown bellow:

module RegBank
#(parameter WIDTH = 4, SIZE = 3)
(
 input                  clk,
 input                  we3,
 input [SIZE-1:0]       A1,
 input [SIZE-1:0]       A2,
 input [SIZE-1:0]       A3,
 input [WIDTH-1:0]      WD3,
 output [WIDTH-1:0] RD1,
 output [WIDTH-1:0] RD2
);

As seen from the interface, its design is flexible for different bus sizes and for the number of internal registers. Both parameters are defined only in the top module of the project, known as Golden Top module.