Welcome to the RISCV_based_processor wiki!

The purpose of this wiki is to externally document the project, giving insights on what it is, how it was developed, the design options and how it works.

Project Scopus and Main Developers

The RISCV_based_processor project is a processor written on Verilog, a hardware description language, and tested on a Field Programmable Gate Array(FPGA). It was developed by a group of brazilian students from EESC - USP (University of Sao Paulo - Brazil) during the course of 1 semester for the modules of SEL0606 - Laboratory of Digital Systems and SSC0902 - Computer Organization and Architecture. The names involved in the project are:

• Enzo Serrano Conti (git: enzoconti, e-mail: enzo.conti@@@usp.br)
• Carlos Craveiro (git: CarlosCraveiro)
• Matheus Cirillo (git: cirillom)
• Matheus Violaro Bellini (git: MatheusVBellini)
• Prof. Dr. Maximilliam Luppe

The project is meant to be a didactic approach to implementing computer architectures via hardware description languages. Its architecture, as the repository's name suggest, is based on the RISC-V instruction set architecture, more specifically on RV32C. The FPGA kit where it was tested, the one which the students had acess, is a DE10Lite kit from Altera(being written on Verilog, it should work on any FPGA, this is only stated so the reader knows the tests were limited to this environment). The project is well documented to serve its didactic purposes. Any doubts or suggestions about the wiki or implementation are welcome and encouraged.

Wiki organization

The project's wiki has the following organization: the Control Unit section discusses everything about the architecture and its implementation on the Control Unit of the processor, while ALU section discusses the implementation and features of its ALU and Register Bank section discusses the registers and the register bank implementation. There is also a Golden Top section that describes the project's main module which instantiates all the other described modules, and a Assembler section that describes the python developed for the processor's instructions. This home section provides only the basic information about the project. All the sections are meant to be descriptive but also elucidating about the project's design options and limitations.