GcnMemHandling - CLRX/CLRX-mirror GitHub Wiki

The instruction or the buffer resource can supply data format in which stored (or will be stored) data. The data format determines format of the pixel (number of components, size of components), the number format determines format of the component.

Below is table with available data formats:

The buffer data format name can be preceded by 'BUF_DATA_FORMAT_' as 'BUF_DATA_FORMAT_8_8'. A data format name is case-insensitive.

The data format 10_11_11 and 11_11_10 seemingly doesn't work correctly on the GCN 1.0 (???)

Below is table with available number formats. The 'BufR' column indicates whether a number format is applicable to read operation, the 'BufW' column indicates whether a number format is applicable to write operation. The 'Reg type' indicates type of vector register (input for writing, output for reading).

The buffer number format name can be preceded by 'BUF_NUM_FORMAT_' as 'BUF_NUM_FORMAT_UNORM'. A number format name is case-insensitive. The FLOAT number float is applicable to 32, 32_32, 32_32_32 or 32_32_32_32 data format. The conversion from integer to floating point value while writing to buffer is doing with rounding to nearest even.

The fields DST_SEL_X, DST_SEL_Y, DST_SEL_Z and DST_SEL_W choose how the source component will be stored into the destination component. DST_SEL_X choose for the first component, DST_SEL_Y for second, DST_SEL_Z for third, DST_SEL_W for fourth. Following values are permitted:

The rules for data conversion for particular instruction types:

• instruction - thing determined from instruction's fields instead of the buffer resource
• derived - data format derived from opcode and ignores resource definition
• identity - choose this same source component for destination component
• resource - thing determined from buffer resource

The address depends on couple factors which are from instruction and the buffer resource. The buffer is organized in simple structure that contains records. Buffer address starts from the base offset given in buffer resource. The index indicates number of the record, and the offset indicates position in record. Expression that describes address:

BUFOFFSET = (UINT32)(AINDEX*STRIDE) + AOFFSET

Optionally, buffer can be addressed in the swizzle mode that is very effective manner to addressing the scratch buffers that holds spilled registers. Expression that describes swizzle mode addressing:

AINDEX_MSB = AINDEX / INDEXSTRIDE
AINDEX_LSB = AINDEX % INDEXSTRIDE
AOFFSET_MSB = AOFFSET / ELEMSIZE
AOFFSET_LSB = AOFFSET % ELEMSIZE
BUFOFFSET = AOFFSET_LSB + ELEMSIZE*AINDEX_LSB + INDEXSTRIDE * (AINDEX_MSB*STRIDE + \
        AOFFSET_MSB * ELEMSIZE)

The expression to calculate element size (ELEMSIZE) from ELEMSIZE field of a buffer resource is: '2<<ELEMSIZE'. The expression to calculate index stride (INDEXSTRIDE) from INDEXSTRIDE field of buffer resource is: '8<<INDEXSTRIDE'.

The 64-bit addressing can be enabled by set ADDR64 flag in instruction. In this case, two VADDR registers contain an address. Expression to calculate address in this case:

ADDRESS = BASE + VGPR_ADDRESS + OFFSET + SGPR_OFFSET // 64-bit addressing

No range checking for 64-bit mode addressing.

The base address are calculated as sum of BASE and SGPR offset. The instruction format supply OFFEN and IDXEN that includes index from VPGR registers. These flags are permitted only if 64-bit addressing is not enabled. Table describes combination of these flags:

Expressions that describes offsets and indices:

UINT32 AOFFSET = OFFSET + (OFFEN ? VGPR_OFFSET : 0)
UINT32 AINDEX = (IDXEN ? VGPR_INDEX : 0) + (TID_ENABLE ? LANEID : 0)

The hardware checks range for buffer resources with STRIDE=0 in following way: if BUFOFFSET >= NUMRECORDS-SGPR_OFFSET then an address is out of range. For STRIDE!=0 if AINDEX >= NUMRECORDS or OFFSET >= STRIDE when IDXEN or TID_ENABLE is set, then an address is out of range. Reads are zero and writes are ignored for addresses out of range.

For 32-bit and wider operations, an address are aligned to 4 bytes. For 16-bit operations, an address are aligned to 2 bytes.

The coalescing works for STRIDE==0 on offset (hardware looks at offset), otherwise it works if stride<=1 or swizzle mode enabled and all offsets are equal and ELEMSIZE has same value as size of element that can be operated by instruction. Then hardware coalesce across any set of contiguous indices for raw buffers. For swizzled buffers, it cannot coalesce across INDEXSTRIDE boundaries.

Reading data to LDS directly is working for BUFFER_LOAD_UBYTE, BUFFER_LOAD_SBYTE, BUFFER_LOAD_SSHORT, BUFFER_LOAD_USHORT, BUFFER_LOAD_DWORD and BUFFER_LOAD_FORMAT_X instructions. If element size is smaller than 4-byte, then stored 4-byte value will be zero-extended. Mixing TFE and LDS flags together is illegal. LDS address are calculated from that expression:

LDS_ADDR = LDS_BASE + (M0&0xffff) + LANEID*4

• LDS_BASE - base address of LDS for wave.
• M0 - M0 register value

The image resource can be a 128-bit (for 2D images, 1D images, 2DMSAA images) or 256 (for 3D images, 2D array of images, 2D cubes and other types).

The 1D images require only width parameter. The 2D images require only width and height parameters. Pitch is optional. The array of 1D images require width, depth (for number of slices), base and last array (BASEARRAY and LASTARRAY) indices for slices. The array of 2D images require width, height, depth (for number of slices), base and last array (BASEARRAY and LASTARRAY) indices for slices. The 3D array images require width, height and depth. The 2D cubes require width, height and base and last array indices of slices. The mipmaps are defined by setting base and last level (BASE_LEVEL and LAST_LEVEL).

The image types list.

Data formats list. The 'ImgR' column indicates whether a number format is applicable to read operation, the 'ImgW' column indicates whether a number format is applicable to write operation. The 'Reg type' indicates type of vector register (input for writing, output for reading).

Number formats list:

The CLAMP mode list:

Depth compare functions list:

The magnification and minification filters list:

The depth and mip filters list:

The border color types list:

The main addressing rules for the images are defined by the tiling registers. The TILINGINDEX choose what register control addressing of image. Index 8 (by default) choose the linear access. In the most cases images are splitted into the tiles which organizes image's data in efficient manner for GPU memory subsystem. Unfortunatelly, the fields of the tiling registers and their meanigful are not known (for me).

The address of image's pixel is stored in VADDR registers. Number of used registers and data type depends on the instruction type and image type. Following table describes what component's of address are stored in VADDR registers for what image types.

The X, Y and Z coordinate's type depends on instruction type. The IMAGE_SAMPLE_* and IMAGE_GATHER4_* accepts floating point values at place of these components. Other instructions accepts unsigned integer values for X, Y and Z components.

The layout of the address is in form:

{ offset } { bias } { z-compare } { derivative } { body } { clamp } { lod }

The body is image address components (X, Y, Z). Other components are used for:

• offset - for IMAGE__O instructions. One dword contains three 6-bit signed offsets for each coordinate (X ,Y, Z) in 0-5 bits (X), 8-13 bits (Y) and 16-21 bits (Z).
• bias - for IMAGE__B instructions. One single floating point value.
• z-compare - for IMAGE__C instructions. One single floating point value. Working only with floating point images.
• derivatives - for IMAGE__D instructions. User supplied derivatives that will be used to calculate LOD. The layout of the derivatives:

• clamp - for IMAGE_*_CL - clamp
• lod - for IMAGE_*_L - LOD

The LOD (Level of details) parameter choose MIPMAP: just the LOD reflects mipmap index. By default, LOD are calculated as maximum value of image's MIN_LOD and sampler's MIN_LOD. The linear MIP filtering get value from two nearest mipmaps to choosen LOD.

About accuracy: Threshold of coordinates for image's sampling are 1/256 of distance between pixels.

The sampling of the mipmaps require normalized coordinates.

By default, FLAT instructions read or write values from main memory. Special register FLAT_SCRATCH defines size and offset of scratch buffer to access scratch space for current wave. Bit fields:

In GCN 1.4 (GFX900, VEGA) architecture FLAT_SCRATCH is 64-bit address of scratch buffer.

The base addresses to access scratch and LDS must be given by driver to some user place.