BlueSCSI SpeedGrade Timings Reference

This document describes the SpeedGrade timing system used to configure SCSI bus timing, PLL clocks, and audio support.

[!NOTE] Updated as of release v2025.10.27

Platform Boot Clocks

Initial clock at MCU reset (before any reclocking):

Platform	Initial Index	Initial Clock
BLUESCSI_MCU_RP23XX	3	150 MHz
BLUESCSI_PICO	1	133 MHz
Other RP2040	0	125 MHz

Automatic Startup Reclocking

Pico-based boards are automatically reclocked at startup to a standardized speed before bluescsi.ini is processed. This ensures consistent SCSI timing across different board variants.

Board Define	Speed Grade Used	Reclocked To
BLUESCSI_PICO_2	SPEED_GRADE_BASE_203MHZ	203.2 MHz
BLUESCSI_MCU_RP20XX	SPEED_GRADE_BASE_203MHZ	203.2 MHz

After startup reclocking, if SpeedGrade= is set in bluescsi.ini to something other than Default, a second reclock occurs to the user-specified speed grade.

Speed Grades

Speed grades are configured via SpeedGrade= in bluescsi.ini.

Index	Enum Name	INI String	Description
0	SPEED_GRADE_DEFAULT	Default	Platform default (no reclocking)
1	SPEED_GRADE_MAX	TurboMax	Maximum performance
2	SPEED_GRADE_CUSTOM	Custom	Load from bluescsi_timings.ini
3	SPEED_GRADE_AUDIO_SPDIF	AudioSPDIF	Optimized for SPDIF audio output
4	SPEED_GRADE_AUDIO_I2S	AudioI2S	Optimized for I2S audio output
5	SPEED_GRADE_A	A	High performance tier
6	SPEED_GRADE_B	B	Medium performance tier
7	SPEED_GRADE_C	C	Lower performance tier
8	SPEED_GRADE_WIFI_RM2	WifiRM2	For external RM2 WiFi module
9	SPEED_GRADE_BASE_203MHZ	(internal)	203.2 MHz base clock
10	SPEED_GRADE_BASE_155MHZ	(internal)	155.25 MHz base clock

Predefined Timing Profiles

Index	Clock (MHz)	Audio Support	Use Case
0	125.0	No	RP2040 default
1	133.0	No	Pico default
2	135.43	Yes (SPDIF)	RP2040 Audio DAC Attack S/PDIF
3	150.0	No	RP2350 default
4	250.0	No	Maximum performance (TurboMax)
5	155.25	Yes	RP2350 with external RM2 WiFi
6	175.0	Yes (I2S)	Alternate I2S audio
7	200.4	Yes (I2S)	Alternate I2S audio
8	251.2	Yes (I2S)	High-speed with I2S audio
9	203.2	Yes	Base clock for I2S and SPDIF over SPI

Speed Grade to Timing Index Mapping

ENABLE_AUDIO_OUTPUT_I2S builds

Speed Grade	INI String	Index	Clock
MAX / A	TurboMax/A	8	251.2
B	B	6	175.0
C	C	5	155.25
AudioSPDIF	AudioSPDIF	9	203.2
AudioI2S	AudioI2S	5	155.25
WifiRM2	WifiRM2	3	150.0

RP2350 (BLUESCSI_MCU_RP23XX) builds

Speed Grade	INI String	Index	Clock
MAX / A	TurboMax/A	4	250.0
B	B	7	200.4
C	C	6	175.0
AudioSPDIF	AudioSPDIF	9	203.2
AudioI2S	AudioI2S	9	203.2

RP2040 builds (default)

Speed Grade	INI String	Index	Clock
MAX / A	TurboMax/A	4	250.0
B	B	3	150.0
C	C	1	133.0
AudioSPDIF	AudioSPDIF	9	203.2
AudioI2S	AudioI2S	9	203.2

Timing Structure

bluescsi_timings_t Fields

typedef struct {
    uint32_t clk_hz;           // System clock frequency in Hz

    struct pll { ... };        // PLL configuration for pico-sdk
    struct scsi { ... };       // General SCSI timing
    struct scsi_20 { ... };    // Ultra SCSI (20 MB/s) timing
    struct scsi_10 { ... };    // Fast SCSI (10 MB/s) timing
    struct scsi_5 { ... };     // SCSI-1 (5 MB/s) timing
    struct sdio { ... };       // SD card interface timing
    struct audio { ... };      // Audio output timing
} bluescsi_timings_t;

SCSI Speed Timing Specs

Parameter	Ultra (20 MB/s)	Fast (10 MB/s)	SCSI-1 (5 MB/s)
delay0	11.5 ns	25 ns	25 ns
delay1	15 ns	30 ns	80 ns
delay2	15 ns	30 ns	80 ns
rdelay1	15 ns	30 ns	80 ns

Delay Definitions

• delay0: Receive hold time - Delay from data write to REQ assertion
• delay1: Transmit assertion time from REQ assert to REQ deassert (REQ pulse width)
• delay2: Negation period (total_period - delay0 - delay1)
• rdelay1: Read transmit assertion time
• rtotal_period_adjust: Adjustment to total delay for rdelay0 calculation
• total_period_adjust: Manual adjustment for scope-verified timing
• max_sync: Minimum sync period supported (value is 1/4 actual ns)

All delay values are in clock cycles minus 1 (for PIO instruction delay).

Custom Timings File

Create bluescsi_timings.ini on the SD card for custom timing configuration.

Sections and Keys

[settings]
disable = 0                    ; Set to 1 to disable custom timings
extends_speed_grade = Default  ; Base speed grade to extend
clk_hz = 125000000            ; Target clock frequency
boot_with_sync_value = 0      ; Force sync period (>0 to enable)
boot_with_offset_value = 15   ; Force offset (0-15)

[pll]
vco_freq_hz = 1500000000      ; VCO frequency (max resulting clock: 252 MHz)
pd1 = 6                       ; Post divider 1
pd2 = 2                       ; Post divider 2
refdiv = 1                    ; Reference divider

[scsi]
clk_period_ps = 8000          ; Clock period in picoseconds
req_delay_cc = 7              ; REQ delay in clock cycles

[scsi_20]                     ; Ultra SCSI timing
delay0_cc = 2                 ; Data setup delay (clock cycles)
delay1_cc = 3                 ; REQ pulse width (clock cycles)
total_period_adjust_cc = -1   ; Period adjustment
max_sync = 12                 ; Max sync value (1/4 ns)
read_delay1_cc = 4            ; Read REQ pulse width
read_total_period_adjust_cc = 0

[scsi_10]                     ; Fast SCSI timing
delay0_cc = 4
delay1_cc = 6
total_period_adjust_cc = -1
max_sync = 25
read_delay1_cc = 6
read_total_period_adjust_cc = 0

[scsi_5]                      ; SCSI-1 timing
delay0_cc = 9
delay1_cc = 14
total_period_adjust_cc = -1
max_sync = 50
read_delay1_cc = 14
read_total_period_adjust_cc = 0

[sdio]
clk_div_pio = 4               ; PIO clock divider
clk_div_1mhz = 25             ; 1MHz reference divider
delay0 = 2
delay1 = 0

[audio]
clk_div_pio = 48              ; Audio PIO divider for 44.1kHz
clk_for_audio = false         ; True if clock supports accurate 44.1kHz

Audio Clock Calculation

For 44.1 kHz audio with 16-bit stereo samples:

clk_div_pio = sys_clk_hz / 16 / 2 / 2 / 44100

Audio is considered "clocked" if the resulting sample rate is within 0.02% of 44.1 kHz.

Global Sync Variables

Set by timing configuration:

extern uint8_t g_max_sync_20_period;  // Ultra SCSI max sync
extern uint8_t g_max_sync_10_period;  // Fast SCSI max sync
extern uint8_t g_max_sync_5_period;   // SCSI-1 max sync
extern uint8_t g_force_sync;          // Forced sync value (0 = auto)
extern uint8_t g_force_offset;        // Forced offset (0-15)